Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\gowin_pll\gowin_pll.v
E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\gowin_pll\gowin_pll_mod.v
E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\key_debounce.v
E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\pll_init.v
E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\test_2k.v
E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\top.v
E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\uhs2_psram_memory_interface\uhs2_psram_memory_interface.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5AR-LV25UG256PC2/I1
Device GW5AR-25
Device Version A
Created Time Wed May 28 14:44:14 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 1s, Peak memory usage = 251.492MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.277s, Peak memory usage = 251.492MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 251.492MB
    Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.199s, Peak memory usage = 251.492MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 251.492MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 251.492MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 251.492MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 251.492MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.128s, Peak memory usage = 251.492MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 251.492MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 251.492MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.859s, Elapsed time = 0h 0m 0.976s, Peak memory usage = 268.043MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.237s, Peak memory usage = 268.336MB
Generate output files:
    CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.554s, Peak memory usage = 268.336MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 268.336MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4294967286
Embedded Port 42
I/O Buf 28
    IBUF 2
    OBUF 4
    TBUF 2
    IOBUF 16
    ELVDS_OBUF 2
    ELVDS_IOBUF 2
Register 2424
    DFFSE 1
    DFFRE 381
    DFFPE 10
    DFFCE 2032
LUT 2213
    LUT2 749
    LUT3 650
    LUT4 814
ALU 230
    ALU 230
INV 41
    INV 41
IOLOGIC 44
    IDES8_MEM 16
    OSER8 4
    OSER8_MEM 20
    IODELAY 4
BSRAM 9
    SDPB 4
    SDPX9B 4
    pROM 1
CLOCK 6
    CLKDIV 1
    DQS 2
    DDRDLL 1
    DHCE 1
    PLLA 1

Resource Utilization Summary

Resource Usage Utilization
Logic 2484(2254 LUT, 230 ALU) / 23040 11%
Register 2424 / 23682 11%
  --Register as Latch 0 / 23682 0%
  --Register as FF 2424 / 23682 11%
BSRAM 9 / 56 17%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
2 u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk Generated 1.905 525.000 0.000 0.952 clk_ibuf/I clk u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
3 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk Generated 7.619 131.250 0.000 3.810 u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0 u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 227.324(MHz) 7 TOP
2 u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0.default_gen_clk 525.000(MHz) 1394.296(MHz) 1 TOP
3 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk 131.250(MHz) 1522.070(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.618
Data Arrival Time 101.634
Data Required Time 100.016
From u_test/error_int1_2_s0
To led_lch_s0
Launch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
99.048 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
99.338 0.290 tCL RR 2300 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
99.638 0.300 tNET RR 1 u_test/error_int1_2_s0/CLK
99.944 0.306 tC2Q RR 1 u_test/error_int1_2_s0/Q
100.244 0.300 tNET RR 1 u_test/error_flag_Z_s0/I0
100.665 0.421 tINS RR 1 u_test/error_flag_Z_s0/F
100.965 0.300 tNET RR 1 u_test/error_flag_Z_s/I2
101.334 0.369 tINS RR 1 u_test/error_flag_Z_s/F
101.634 0.300 tNET RR 1 led_lch_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 clk
100.000 0.000 tCL RR 1 clk_ibuf/I
100.000 0.000 tINS RR 185 clk_ibuf/O
100.300 0.300 tNET RR 1 led_lch_s0/CLK
100.265 -0.035 tUnc led_lch_s0
100.016 -0.249 tSu 1 led_lch_s0
Path Statistics:
Clock Skew: -0.290
Setup Relationship: 0.952
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.790, 39.579%; route: 0.900, 45.090%; tC2Q: 0.306, 15.331%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 2

Path Summary:
Slack -1.412
Data Arrival Time 101.626
Data Required Time 100.214
From inst_apm64_top/u_apm64_top/init_calib_done_s0
To led_cnt_24_s0
Launch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
99.048 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
99.338 0.290 tCL RR 2300 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
99.638 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/init_calib_done_s0/CLK
99.944 0.306 tC2Q RR 18 inst_apm64_top/u_apm64_top/init_calib_done_s0/Q
100.244 0.300 tNET RR 1 n84_s3/I1
100.657 0.413 tINS RR 11 n84_s3/F
100.957 0.300 tNET RR 1 n60_s2/I2
101.326 0.369 tINS RR 1 n60_s2/F
101.626 0.300 tNET RR 1 led_cnt_24_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 clk
100.000 0.000 tCL RR 1 clk_ibuf/I
100.000 0.000 tINS RR 185 clk_ibuf/O
100.300 0.300 tNET RR 1 led_cnt_24_s0/CLK
100.265 -0.035 tUnc led_cnt_24_s0
100.214 -0.051 tSu 1 led_cnt_24_s0
Path Statistics:
Clock Skew: -0.290
Setup Relationship: 0.952
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.782, 39.336%; route: 0.900, 45.272%; tC2Q: 0.306, 15.392%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 3

Path Summary:
Slack -1.253
Data Arrival Time 101.467
Data Required Time 100.214
From inst_apm64_top/u_apm64_top/init_calib_done_s0
To led_cnt_2_s0
Launch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
99.048 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
99.338 0.290 tCL RR 2300 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
99.638 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/init_calib_done_s0/CLK
99.944 0.306 tC2Q RR 18 inst_apm64_top/u_apm64_top/init_calib_done_s0/Q
100.244 0.300 tNET RR 1 n84_s3/I1
100.657 0.413 tINS RR 11 n84_s3/F
100.957 0.300 tNET RR 1 n82_s2/I3
101.167 0.210 tINS RR 1 n82_s2/F
101.467 0.300 tNET RR 1 led_cnt_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 clk
100.000 0.000 tCL RR 1 clk_ibuf/I
100.000 0.000 tINS RR 185 clk_ibuf/O
100.300 0.300 tNET RR 1 led_cnt_2_s0/CLK
100.265 -0.035 tUnc led_cnt_2_s0
100.214 -0.051 tSu 1 led_cnt_2_s0
Path Statistics:
Clock Skew: -0.290
Setup Relationship: 0.952
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.623, 34.062%; route: 0.900, 49.208%; tC2Q: 0.306, 16.730%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 4

Path Summary:
Slack -1.253
Data Arrival Time 101.467
Data Required Time 100.214
From inst_apm64_top/u_apm64_top/init_calib_done_s0
To led_cnt_5_s0
Launch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
99.048 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
99.338 0.290 tCL RR 2300 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
99.638 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/init_calib_done_s0/CLK
99.944 0.306 tC2Q RR 18 inst_apm64_top/u_apm64_top/init_calib_done_s0/Q
100.244 0.300 tNET RR 1 n84_s3/I1
100.657 0.413 tINS RR 11 n84_s3/F
100.957 0.300 tNET RR 1 n79_s2/I3
101.167 0.210 tINS RR 1 n79_s2/F
101.467 0.300 tNET RR 1 led_cnt_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 clk
100.000 0.000 tCL RR 1 clk_ibuf/I
100.000 0.000 tINS RR 185 clk_ibuf/O
100.300 0.300 tNET RR 1 led_cnt_5_s0/CLK
100.265 -0.035 tUnc led_cnt_5_s0
100.214 -0.051 tSu 1 led_cnt_5_s0
Path Statistics:
Clock Skew: -0.290
Setup Relationship: 0.952
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.623, 34.062%; route: 0.900, 49.208%; tC2Q: 0.306, 16.730%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%

Path 5

Path Summary:
Slack -1.253
Data Arrival Time 101.467
Data Required Time 100.214
From inst_apm64_top/u_apm64_top/init_calib_done_s0
To led_cnt_8_s0
Launch Clk inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
99.048 0.000 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT.default_gen_clk
99.338 0.290 tCL RR 2300 inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
99.638 0.300 tNET RR 1 inst_apm64_top/u_apm64_top/init_calib_done_s0/CLK
99.944 0.306 tC2Q RR 18 inst_apm64_top/u_apm64_top/init_calib_done_s0/Q
100.244 0.300 tNET RR 1 n84_s3/I1
100.657 0.413 tINS RR 11 n84_s3/F
100.957 0.300 tNET RR 1 n76_s2/I3
101.167 0.210 tINS RR 1 n76_s2/F
101.467 0.300 tNET RR 1 led_cnt_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
100.000 0.000 clk
100.000 0.000 tCL RR 1 clk_ibuf/I
100.000 0.000 tINS RR 185 clk_ibuf/O
100.300 0.300 tNET RR 1 led_cnt_8_s0/CLK
100.265 -0.035 tUnc led_cnt_8_s0
100.214 -0.051 tSu 1 led_cnt_8_s0
Path Statistics:
Clock Skew: -0.290
Setup Relationship: 0.952
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%
Arrival Data Path Delay: cell: 0.623, 34.062%; route: 0.900, 49.208%; tC2Q: 0.306, 16.730%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.300, 100.000%