Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.cst
Timing Constraint File	E:\IP\PSRAM\UHS2_Memory_Interface\RefDesign\Gowin_UHS2_PSRAM_Memory_Interface_RefDesign\project\src\psram.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW5AR-LV25UG256PC2/I1
Device	GW5AR-25
Device Version	A
Created Time	Wed May 28 14:44:37 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	9614
Numbers of Endpoints Analyzed	8623
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	mem_clk	Base	1.875	533.333	0.000	0.938			memory_clk
2	clkin	Base	20.000	50.000	0.000	10.000			clk
3	userclk	Generated	7.500	133.333	0.000	3.750	memory_clk	mem_clk	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	mem_clk	533.333(MHz)	2338.896(MHz)	1	TOP
2	clkin	50.000(MHz)	218.102(MHz)	7	TOP
3	userclk	133.333(MHz)	158.654(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
mem_clk	Setup	0.000	0
mem_clk	Hold	0.000	0
clkin	Setup	0.000	0
clkin	Hold	0.000	0
userclk	Setup	0.000	0
userclk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.197	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0/D	userclk:[R]	userclk:[R]	7.500	0.000	6.252
2	1.284	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/D	userclk:[R]	userclk:[R]	7.500	0.000	6.165
3	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
4	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
5	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
6	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
7	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
8	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
9	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
10	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
11	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
12	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
13	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
14	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
15	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
16	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
17	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
18	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
19	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
20	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
21	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
22	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
23	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[0]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
24	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[2]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428
25	1.447	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[1]	mem_clk:[R]	mem_clk:[R]	1.875	0.000	0.428

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.155	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D0	userclk:[R]	userclk:[R]	0.000	-0.002	0.239
2	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
3	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
4	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
5	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
6	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
7	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
8	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
9	0.275	u_test/addr_11_s1/Q	u_test/addr_11_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
10	0.275	u_test/wcnt_2_s1/Q	u_test/wcnt_2_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
11	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
12	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
13	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
14	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
15	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
16	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
17	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
18	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
19	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
20	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
21	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
22	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
23	0.275	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
24	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300
25	0.275	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0/D	userclk:[R]	userclk:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	17.816	u_reset_key/key_1_s0/Q	led_cnt_24_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.017	1.889
2	17.816	u_reset_key/key_1_s0/Q	led_cnt_0_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.017	1.889
3	17.816	u_reset_key/key_1_s0/Q	led_cnt_9_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.017	1.889
4	17.816	u_reset_key/key_1_s0/Q	led_cnt_22_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.017	1.889
5	17.816	u_reset_key/key_1_s0/Q	led_cnt_23_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.017	1.889
6	17.819	u_reset_key/key_1_s0/Q	led_err_s2/CLEAR	clkin:[R]	clkin:[R]	20.000	0.006	1.896
7	17.819	u_reset_key/key_1_s0/Q	led_cnt_7_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.012	1.890
8	17.819	u_reset_key/key_1_s0/Q	led_cnt_17_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.012	1.890
9	17.819	u_reset_key/key_1_s0/Q	led_cnt_21_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.012	1.890
10	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLEAR	clkin:[R]	clkin:[R]	20.000	0.019	1.879
11	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3/CLEAR	clkin:[R]	clkin:[R]	20.000	0.019	1.879
12	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
13	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_2_s1/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
14	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_11_s1/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
15	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.019	1.879
16	17.824	u_reset_key/key_1_s0/Q	led_lch_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
17	17.824	u_reset_key/key_1_s0/Q	led_cnt_1_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
18	17.824	u_reset_key/key_1_s0/Q	led_cnt_2_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
19	17.824	u_reset_key/key_1_s0/Q	led_cnt_14_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.009	1.889
20	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_3_s1/CLEAR	clkin:[R]	clkin:[R]	20.000	0.014	1.884
21	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1/CLEAR	clkin:[R]	clkin:[R]	20.000	0.014	1.884
22	17.824	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_d2_s0/CLEAR	clkin:[R]	clkin:[R]	20.000	0.014	1.884
23	17.827	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR	clkin:[R]	clkin:[R]	20.000	0.004	1.890
24	17.827	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLEAR	clkin:[R]	clkin:[R]	20.000	0.003	1.892
25	17.827	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLEAR	clkin:[R]	clkin:[R]	20.000	0.004	1.890

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.989	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_3_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.007	0.929
2	0.989	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.007	0.929
3	0.989	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_5_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.007	0.929
4	0.993	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.003	0.943
5	0.993	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_2_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.003	0.943
6	0.993	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_1_s2/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.008	0.948
7	0.995	u_reset_key/key_1_s0/Q	led_cnt_6_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.000	0.942
8	0.995	u_reset_key/key_1_s0/Q	led_cnt_8_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.000	0.942
9	0.995	u_reset_key/key_1_s0/Q	led_cnt_19_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.000	0.942
10	0.995	u_reset_key/key_1_s0/Q	led_cnt_20_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.000	0.942
11	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.015	0.958
12	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_1_s0/PRESET	clkin:[R]	clkin:[R]	0.000	-0.015	0.958
13	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/count_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.017	0.960
14	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/count_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.017	0.960
15	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/count_2_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.017	0.960
16	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/PRESET	clkin:[R]	clkin:[R]	0.000	-0.019	0.961
17	0.996	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.019	0.961
18	0.996	u_reset_key/key_1_s0/Q	u_Gowin_PLL/u_pll_init/rEnable_1_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.019	0.961
19	0.996	u_reset_key/key_1_s0/Q	u_Gowin_PLL/u_pll_init/rEnable_0_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	-0.019	0.961
20	0.998	u_reset_key/key_1_s0/Q	led_cnt_3_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.004	0.941
21	0.998	u_reset_key/key_1_s0/Q	led_cnt_4_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.004	0.941
22	0.998	u_reset_key/key_1_s0/Q	led_cnt_13_s0/CLEAR	clkin:[R]	clkin:[R]	0.000	0.004	0.941
23	0.999	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR	clkin:[R]	clkin:[R]	0.000	0.004	0.942
24	0.999	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLEAR	clkin:[R]	clkin:[R]	0.000	0.004	0.942
25	0.999	u_reset_key/key_1_s0/Q	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1/CLEAR	clkin:[R]	clkin:[R]	0.000	0.004	0.942

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s
2	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s
3	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s
4	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s
5	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s
6	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
7	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s
8	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s
9	2.040	2.902	0.862	Low Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s
10	2.042	2.904	0.862	High Pulse Width	userclk	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.197
Data Arrival Time	7.769
Data Required Time	8.966
From	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.517	1.517	tNET	RR	1	R30C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0/CLK
1.823	0.306	tC2Q	RR	338	R30C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0/Q
3.598	1.775	tNET	RR	1	R32C17[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s0/I3
4.011	0.413	tINS	RR	13	R32C17[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s0/F
6.120	2.109	tNET	RR	1	R9C10[3][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s5/I3
6.537	0.417	tINS	RR	3	R9C10[3][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s5/F
6.800	0.263	tNET	RR	2	R11C10[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n70_s0/I1
7.250	0.450	tINS	RF	1	R11C10[1][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n70_s0/COUT
7.559	0.309	tNET	FF	1	R12C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_rempty_val_s1/I0
7.769	0.210	tINS	FR	1	R12C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_rempty_val_s1/F
7.769	0.000	tNET	RR	1	R12C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					userclk
7.500	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.017	1.517	tNET	RR	1	R12C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0/CLK
8.966	-0.051	tSu		1	R12C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Empty_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	7.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.517, 100.000%
Arrival Data Path Delay	cell: 1.490, 23.832%; route: 4.456, 71.273%; tC2Q: 0.306, 4.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.517, 100.000%

Path2

Path Summary:

Slack	1.284
Data Arrival Time	7.682
Data Required Time	8.966
From	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.517	1.517	tNET	RR	1	R30C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0/CLK
1.823	0.306	tC2Q	RR	338	R30C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/init_calib_s0/Q
3.598	1.775	tNET	RR	1	R32C17[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s0/I3
4.011	0.413	tINS	RR	13	R32C17[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/n51_s0/F
6.120	2.109	tNET	RR	1	R9C10[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s4/I2
6.541	0.421	tINS	RR	2	R9C10[2][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_2_s4/F
6.545	0.004	tNET	RR	1	R9C10[2][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_3_s2/I1
6.914	0.369	tINS	RR	3	R9C10[2][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wbinnext_3_s2/F
7.313	0.399	tNET	RR	1	R12C10[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wfull_val_s0/I2
7.682	0.369	tINS	RR	1	R12C10[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_wfull_val_s0/F
7.682	0.000	tNET	RR	1	R12C10[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.500	7.500					active clock edge time
7.500	0.000					userclk
7.500	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
9.017	1.517	tNET	RR	1	R12C10[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0/CLK
8.966	-0.051	tSu		1	R12C10[0][B]	inst_apm64_top/u_apm64_top/u_apsram_wd/u_fifo_ctrl/of_Full_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	7.500
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.517, 100.000%
Arrival Data Path Delay	cell: 1.572, 25.499%; route: 4.287, 69.538%; tC2Q: 0.306, 4.964%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.517, 100.000%

Path3

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path4

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path5

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT70[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[7].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path6

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path7

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path8

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT70[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[6].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path9

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path10

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path11

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT68[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[5].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path12

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path13

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path14

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT68[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[4].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path15

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path16

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path17

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT66[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[3].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path18

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path19

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path20

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT66[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[2].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path21

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path22

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path23

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[0]
0.937	0.000	tNET	FF	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/RADDR[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT63[B]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[1].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path24

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[2]
0.937	0.000	tNET	FF	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Path25

Path Summary:

Slack	1.447
Data Arrival Time	0.937
Data Required Time	2.385
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem
Launch Clk	mem_clk:[R]
Latch Clk	mem_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					mem_clk
0.000	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
0.000	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
0.157	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
0.510	0.353	tNET	RR	5	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/FCLK
0.937	0.428	tC2Q	RF	8	R0C60	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs/RPOINT[1]
0.937	0.000	tNET	FF	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/RADDR[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1.875	1.875					active clock edge time
1.875	0.000					mem_clk
1.875	0.000	tCL	RR	1	PLL_T	u_Gowin_PLL/u_pll/PLLA_inst/CLKOUT0
1.875	0.000	tNET	RR	3	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKIN
2.032	0.157	tINS	RR	44	R0C65	inst_apm64_top/u_apm64_top/u_dqce_clk_x4/CLKOUT
2.385	0.353	tNET	RR	1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem/FCLK
2.385	0.000	tSu		1	IOT63[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/iserdes_gen[0].u_ides8_mem

Path Statistics:

Clock Skew	0.000
Setup Relationship	1.875
Logic Level	1
Arrival Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.428, 100.000%
Required Clock Path Delay	cell: 0.157, 30.769%; route: 0.353, 69.231%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.155
Data Arrival Time	0.959
Data Required Time	0.803
From	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0
To	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.720	0.720	tNET	RR	1	R2C61[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0/CLK
0.864	0.144	tC2Q	RR	2	R2C61[0][A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/dqs_dx_0_s0/Q
0.959	0.095	tNET	RR	1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722	0.722	tNET	RR	1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen/PCLK
0.803	0.082	tHld		1	IOT61[A]	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_dqs_gen

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.095, 39.749%; tC2Q: 0.144, 60.251%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%

Path2

Path Summary:

Slack	0.275
Data Arrival Time	1.010
Data Required Time	0.735
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3/CLK
0.852	0.141	tC2Q	RF	5	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3/Q
0.858	0.006	tNET	FF	1	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1130_s4/I2
1.010	0.153	tINS	FF	1	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1130_s4/F
1.010	0.000	tNET	FF	1	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3/CLK
0.735	0.025	tHld		1	R23C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%

Path3

Path Summary:

Slack	0.275
Data Arrival Time	1.010
Data Required Time	0.735
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4/CLK
0.852	0.141	tC2Q	RF	2	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4/Q
0.858	0.006	tNET	FF	1	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1124_s6/I2
1.010	0.153	tINS	FF	1	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1124_s6/F
1.010	0.000	tNET	FF	1	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4/CLK
0.735	0.025	tHld		1	R23C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/burst_cnt_7_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	1.016
Data Required Time	0.741
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.716	0.716	tNET	RR	1	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0/CLK
0.857	0.141	tC2Q	RF	3	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0/Q
0.863	0.006	tNET	FF	1	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n237_s1/I0
1.016	0.153	tINS	FF	1	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n237_s1/F
1.016	0.000	tNET	FF	1	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.716	0.716	tNET	RR	1	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0/CLK
0.741	0.025	tHld		1	R20C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXHS_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.716, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.716, 100.000%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	1.011
Data Required Time	0.736
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0/CLK
0.852	0.141	tC2Q	RF	3	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0/Q
0.858	0.006	tNET	FF	1	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n82_s3/I0
1.011	0.153	tINS	FF	1	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n82_s3/F
1.011	0.000	tNET	FF	1	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.711	0.711	tNET	RR	1	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0/CLK
0.736	0.025	tHld		1	R25C5[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tXSR_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.711, 100.000%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	1.001
Data Required Time	0.726
From	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1/CLK
0.842	0.141	tC2Q	RF	5	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1/Q
0.848	0.006	tNET	FF	1	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1065_s1/I0
1.001	0.153	tINS	FF	1	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1065_s1/F
1.001	0.000	tNET	FF	1	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.701	0.701	tNET	RR	1	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1/CLK
0.726	0.025	tHld		1	R27C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.010
Data Required Time	0.735
From	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.710	0.710	tNET	RR	1	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0/CLK
0.851	0.141	tC2Q	RF	5	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0/Q
0.857	0.006	tNET	FF	1	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2528_s2/I0
1.010	0.153	tINS	FF	1	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2528_s2/F
1.010	0.000	tNET	FF	1	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.710	0.710	tNET	RR	1	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0/CLK
0.735	0.025	tHld		1	R26C32[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/read_calibration[0].cal_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.710, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.710, 100.000%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.010
Data Required Time	0.735
From	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.710	0.710	tNET	RR	1	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0/CLK
0.851	0.141	tC2Q	RF	4	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0/Q
0.857	0.006	tNET	FF	1	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1193_s1/I3
1.010	0.153	tINS	FF	1	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1193_s1/F
1.010	0.000	tNET	FF	1	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.710	0.710	tNET	RR	1	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0/CLK
0.735	0.025	tHld		1	R26C28[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tRST_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.710, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.710, 100.000%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	0.982
Data Required Time	0.707
From	u_test/addr_11_s1
To	u_test/addr_11_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R30C15[0][A]	u_test/addr_11_s1/CLK
0.823	0.141	tC2Q	RF	6	R30C15[0][A]	u_test/addr_11_s1/Q
0.829	0.006	tNET	FF	1	R30C15[0][A]	u_test/n1393_s3/I3
0.982	0.153	tINS	FF	1	R30C15[0][A]	u_test/n1393_s3/F
0.982	0.000	tNET	FF	1	R30C15[0][A]	u_test/addr_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R30C15[0][A]	u_test/addr_11_s1/CLK
0.707	0.025	tHld		1	R30C15[0][A]	u_test/addr_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	0.998
Data Required Time	0.723
From	u_test/wcnt_2_s1
To	u_test/wcnt_2_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.698	0.698	tNET	RR	1	R33C20[0][A]	u_test/wcnt_2_s1/CLK
0.839	0.141	tC2Q	RF	36	R33C20[0][A]	u_test/wcnt_2_s1/Q
0.845	0.006	tNET	FF	1	R33C20[0][A]	u_test/n1475_s1/I2
0.998	0.153	tINS	FF	1	R33C20[0][A]	u_test/n1475_s1/F
0.998	0.000	tNET	FF	1	R33C20[0][A]	u_test/wcnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.698	0.698	tNET	RR	1	R33C20[0][A]	u_test/wcnt_2_s1/CLK
0.723	0.025	tHld		1	R33C20[0][A]	u_test/wcnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.698, 100.000%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	0.978
Data Required Time	0.703
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0/CLK
0.819	0.141	tC2Q	RF	5	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0/Q
0.825	0.006	tNET	FF	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1474_s2/I0
0.978	0.153	tINS	FF	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1474_s2/F
0.978	0.000	tNET	FF	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.678	0.678	tNET	RR	1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0/CLK
0.703	0.025	tHld		1	R30C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.678, 100.000%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0/CLK
0.831	0.141	tC2Q	RF	2	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0/Q
0.837	0.006	tNET	FF	1	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1441_s1/I3
0.990	0.153	tINS	FF	1	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1441_s1/F
0.990	0.000	tNET	FF	1	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0/CLK
0.715	0.025	tHld		1	R33C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/prescaler_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	0.982
Data Required Time	0.707
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0/CLK
0.823	0.141	tC2Q	RF	6	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0/Q
0.829	0.006	tNET	FF	1	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n143_s3/I0
0.982	0.153	tINS	FF	1	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n143_s3/F
0.982	0.000	tNET	FF	1	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0/CLK
0.707	0.025	tHld		1	R31C6[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	0.986
Data Required Time	0.711
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/CLK
0.827	0.141	tC2Q	RF	4	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/Q
0.833	0.006	tNET	FF	1	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n141_s3/I1
0.986	0.153	tINS	FF	1	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n141_s3/F
0.986	0.000	tNET	FF	1	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0/CLK
0.711	0.025	tHld		1	R31C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/CLK
0.831	0.141	tC2Q	RF	3	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/Q
0.837	0.006	tNET	FF	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n140_s1/I3
0.990	0.153	tINS	FF	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n140_s1/F
0.990	0.000	tNET	FF	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0/CLK
0.715	0.025	tHld		1	R32C7[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	0.986
Data Required Time	0.711
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/CLK
0.827	0.141	tC2Q	RF	3	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/Q
0.833	0.006	tNET	FF	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n136_s1/I3
0.986	0.153	tINS	FF	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n136_s1/F
0.986	0.000	tNET	FF	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.686	0.686	tNET	RR	1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0/CLK
0.711	0.025	tHld		1	R32C6[1][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0/CLK
0.831	0.141	tC2Q	RF	4	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0/Q
0.837	0.006	tNET	FF	1	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n134_s1/I3
0.990	0.153	tINS	FF	1	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n134_s1/F
0.990	0.000	tNET	FF	1	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0/CLK
0.715	0.025	tHld		1	R31C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tHS_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	0.991
Data Required Time	0.716
From	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691	0.691	tNET	RR	1	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1/CLK
0.832	0.141	tC2Q	RF	6	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1/Q
0.838	0.006	tNET	FF	1	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1532_s3/I1
0.991	0.153	tINS	FF	1	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1532_s3/F
0.991	0.000	tNET	FF	1	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691	0.691	tNET	RR	1	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1/CLK
0.716	0.025	tHld		1	R29C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt0_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1/CLK
0.831	0.141	tC2Q	RF	2	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1/Q
0.837	0.006	tNET	FF	1	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1272_s2/I2
0.990	0.153	tINS	FF	1	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1272_s2/F
0.990	0.000	tNET	FF	1	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1/CLK
0.715	0.025	tHld		1	R32C29[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tWRW_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	0.982
Data Required Time	0.707
From	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1
To	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1/CLK
0.823	0.141	tC2Q	RF	5	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1/Q
0.829	0.006	tNET	FF	1	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1064_s3/I0
0.982	0.153	tINS	FF	1	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1064_s3/F
0.982	0.000	tNET	FF	1	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.682	0.682	tNET	RR	1	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1/CLK
0.707	0.025	tHld		1	R30C23[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/tpu_cnt_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.682, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0/CLK
0.831	0.141	tC2Q	RF	6	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0/Q
0.837	0.006	tNET	FF	1	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2465_s1/I1
0.990	0.153	tINS	FF	1	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n2465_s1/F
0.990	0.000	tNET	FF	1	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0/CLK
0.715	0.025	tHld		1	R33C26[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/timer_cnt1_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	0.990
Data Required Time	0.715
From	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0/CLK
0.831	0.141	tC2Q	RF	3	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0/Q
0.837	0.006	tNET	FF	1	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1132_s2/I0
0.990	0.153	tINS	FF	1	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n1132_s2/F
0.990	0.000	tNET	FF	1	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.690	0.690	tNET	RR	1	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0/CLK
0.715	0.025	tHld		1	R32C21[1][A]	inst_apm64_top/u_apm64_top/u_apsram_init/stable_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.690, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	0.991
Data Required Time	0.716
From	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0
To	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691	0.691	tNET	RR	1	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0/CLK
0.832	0.141	tC2Q	RF	6	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0/Q
0.838	0.006	tNET	FF	1	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n_state_2_s20/I3
0.991	0.153	tINS	FF	1	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/n_state_2_s20/F
0.991	0.000	tNET	FF	1	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.691	0.691	tNET	RR	1	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0/CLK
0.716	0.025	tHld		1	R29C23[0][A]	inst_apm64_top/u_apm64_top/u_apsram_init/c_state_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.022
Data Required Time	0.747
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722	0.722	tNET	RR	1	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/CLK
0.863	0.141	tC2Q	RF	3	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/Q
0.869	0.006	tNET	FF	1	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1325_s1/I2
1.022	0.153	tINS	FF	1	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1325_s1/F
1.022	0.000	tNET	FF	1	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.722	0.722	tNET	RR	1	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1/CLK
0.747	0.025	tHld		1	R21C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/tcphr_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.722, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.006
Data Required Time	0.731
From	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0
To	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0
Launch Clk	userclk:[R]
Latch Clk	userclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.706	0.706	tNET	RR	1	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0/CLK
0.847	0.141	tC2Q	RF	2	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0/Q
0.853	0.006	tNET	FF	1	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1470_s1/I3
1.006	0.153	tINS	FF	1	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/n1470_s1/F
1.006	0.000	tNET	FF	1	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					userclk
0.000	0.000	tCL	RR	2316	TOPSIDE[0]	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
0.706	0.706	tNET	RR	1	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0/CLK
0.731	0.025	tHld		1	R26C5[0][A]	inst_apm64_top/u_apm64_top/u_apsram_ctrl/refresh_timer_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.706, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.706, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	17.816
Data Arrival Time	4.021
Data Required Time	21.837
From	u_reset_key/key_1_s0
To	led_cnt_24_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C7[1][B]	led_cnt_24_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.115	1.528	tNET	RR	1	R14C7[1][B]	led_cnt_24_s0/CLK
21.837	-0.278	tSu		1	R14C7[1][B]	led_cnt_24_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.749%; route: 1.528, 72.251%

Path2

Path Summary:

Slack	17.816
Data Arrival Time	4.021
Data Required Time	21.837
From	u_reset_key/key_1_s0
To	led_cnt_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C7[0][A]	led_cnt_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.115	1.528	tNET	RR	1	R14C7[0][A]	led_cnt_0_s0/CLK
21.837	-0.278	tSu		1	R14C7[0][A]	led_cnt_0_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.749%; route: 1.528, 72.251%

Path3

Path Summary:

Slack	17.816
Data Arrival Time	4.021
Data Required Time	21.837
From	u_reset_key/key_1_s0
To	led_cnt_9_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C7[1][A]	led_cnt_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.115	1.528	tNET	RR	1	R14C7[1][A]	led_cnt_9_s0/CLK
21.837	-0.278	tSu		1	R14C7[1][A]	led_cnt_9_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.749%; route: 1.528, 72.251%

Path4

Path Summary:

Slack	17.816
Data Arrival Time	4.021
Data Required Time	21.837
From	u_reset_key/key_1_s0
To	led_cnt_22_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C7[0][B]	led_cnt_22_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.115	1.528	tNET	RR	1	R14C7[0][B]	led_cnt_22_s0/CLK
21.837	-0.278	tSu		1	R14C7[0][B]	led_cnt_22_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.749%; route: 1.528, 72.251%

Path5

Path Summary:

Slack	17.816
Data Arrival Time	4.021
Data Required Time	21.837
From	u_reset_key/key_1_s0
To	led_cnt_23_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C7[2][A]	led_cnt_23_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.115	1.528	tNET	RR	1	R14C7[2][A]	led_cnt_23_s0/CLK
21.837	-0.278	tSu		1	R14C7[2][A]	led_cnt_23_s0

Path Statistics:

Clock Skew	-0.017
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.749%; route: 1.528, 72.251%

Path6

Path Summary:

Slack	17.819
Data Arrival Time	4.028
Data Required Time	21.848
From	u_reset_key/key_1_s0
To	led_err_s2
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.028	1.602	tNET	FF	1	IOB6[B]	led_err_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.126	1.539	tNET	RR	1	IOB6[B]	led_err_s2/CLK
21.848	-0.278	tSu		1	IOB6[B]	led_err_s2

Path Statistics:

Clock Skew	-0.006
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.602, 84.498%; tC2Q: 0.294, 15.502%
Required Clock Path Delay	cell: 0.587, 27.609%; route: 1.539, 72.391%

Path7

Path Summary:

Slack	17.819
Data Arrival Time	4.022
Data Required Time	21.842
From	u_reset_key/key_1_s0
To	led_cnt_7_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.022	1.596	tNET	FF	1	R15C7[1][A]	led_cnt_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.120	1.533	tNET	RR	1	R15C7[1][A]	led_cnt_7_s0/CLK
21.842	-0.278	tSu		1	R15C7[1][A]	led_cnt_7_s0

Path Statistics:

Clock Skew	-0.012
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.596, 84.449%; tC2Q: 0.294, 15.551%
Required Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%

Path8

Path Summary:

Slack	17.819
Data Arrival Time	4.022
Data Required Time	21.842
From	u_reset_key/key_1_s0
To	led_cnt_17_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.022	1.596	tNET	FF	1	R15C7[0][B]	led_cnt_17_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.120	1.533	tNET	RR	1	R15C7[0][B]	led_cnt_17_s0/CLK
21.842	-0.278	tSu		1	R15C7[0][B]	led_cnt_17_s0

Path Statistics:

Clock Skew	-0.012
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.596, 84.449%; tC2Q: 0.294, 15.551%
Required Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%

Path9

Path Summary:

Slack	17.819
Data Arrival Time	4.022
Data Required Time	21.842
From	u_reset_key/key_1_s0
To	led_cnt_21_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.022	1.596	tNET	FF	1	R15C7[0][A]	led_cnt_21_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.120	1.533	tNET	RR	1	R15C7[0][A]	led_cnt_21_s0/CLK
21.842	-0.278	tSu		1	R15C7[0][A]	led_cnt_21_s0

Path Statistics:

Clock Skew	-0.012
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.596, 84.449%; tC2Q: 0.294, 15.551%
Required Clock Path Delay	cell: 0.587, 27.687%; route: 1.533, 72.313%

Path10

Path Summary:

Slack	17.824
Data Arrival Time	4.011
Data Required Time	21.835
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.011	1.585	tNET	FF	1	R12C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.113	1.526	tNET	RR	1	R12C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3/CLK
21.835	-0.278	tSu		1	R12C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_0_s3

Path Statistics:

Clock Skew	-0.019
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.585, 84.358%; tC2Q: 0.294, 15.642%
Required Clock Path Delay	cell: 0.587, 27.775%; route: 1.526, 72.225%

Path11

Path Summary:

Slack	17.824
Data Arrival Time	4.011
Data Required Time	21.835
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.011	1.585	tNET	FF	1	R12C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.113	1.526	tNET	RR	1	R12C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3/CLK
21.835	-0.278	tSu		1	R12C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_1_s3

Path Statistics:

Clock Skew	-0.019
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.585, 84.358%; tC2Q: 0.294, 15.642%
Required Clock Path Delay	cell: 0.587, 27.775%; route: 1.526, 72.225%

Path12

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3/CLK
21.845	-0.278	tSu		1	R14C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_10_s3

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path13

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_2_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_2_s1/CLK
21.845	-0.278	tSu		1	R14C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_2_s1

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path14

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_11_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_11_s1/CLK
21.845	-0.278	tSu		1	R14C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_11_s1

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path15

Path Summary:

Slack	17.824
Data Arrival Time	4.011
Data Required Time	21.835
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.011	1.585	tNET	FF	1	R12C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.113	1.526	tNET	RR	1	R12C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0/CLK
21.835	-0.278	tSu		1	R12C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_1_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.585, 84.358%; tC2Q: 0.294, 15.642%
Required Clock Path Delay	cell: 0.587, 27.775%; route: 1.526, 72.225%

Path16

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	led_lch_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C6[1][B]	led_lch_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C6[1][B]	led_lch_s0/CLK
21.845	-0.278	tSu		1	R14C6[1][B]	led_lch_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path17

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	led_cnt_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C6[2][A]	led_cnt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C6[2][A]	led_cnt_1_s0/CLK
21.845	-0.278	tSu		1	R14C6[2][A]	led_cnt_1_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path18

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	led_cnt_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C6[2][B]	led_cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C6[2][B]	led_cnt_2_s0/CLK
21.845	-0.278	tSu		1	R14C6[2][B]	led_cnt_2_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path19

Path Summary:

Slack	17.824
Data Arrival Time	4.021
Data Required Time	21.845
From	u_reset_key/key_1_s0
To	led_cnt_14_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.021	1.595	tNET	FF	1	R14C6[0][B]	led_cnt_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.123	1.536	tNET	RR	1	R14C6[0][B]	led_cnt_14_s0/CLK
21.845	-0.278	tSu		1	R14C6[0][B]	led_cnt_14_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.595, 84.436%; tC2Q: 0.294, 15.564%
Required Clock Path Delay	cell: 0.587, 27.651%; route: 1.536, 72.349%

Path20

Path Summary:

Slack	17.824
Data Arrival Time	4.016
Data Required Time	21.840
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_3_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.016	1.590	tNET	FF	1	R13C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.118	1.531	tNET	RR	1	R13C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_3_s1/CLK
21.840	-0.278	tSu		1	R13C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_3_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.590, 84.397%; tC2Q: 0.294, 15.603%
Required Clock Path Delay	cell: 0.587, 27.713%; route: 1.531, 72.287%

Path21

Path Summary:

Slack	17.824
Data Arrival Time	4.016
Data Required Time	21.840
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.016	1.590	tNET	FF	1	R13C8[2][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.118	1.531	tNET	RR	1	R13C8[2][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1/CLK
21.840	-0.278	tSu		1	R13C8[2][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_6_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.590, 84.397%; tC2Q: 0.294, 15.603%
Required Clock Path Delay	cell: 0.587, 27.713%; route: 1.531, 72.287%

Path22

Path Summary:

Slack	17.824
Data Arrival Time	4.016
Data Required Time	21.840
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_d2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.016	1.590	tNET	FF	1	R13C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_d2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.118	1.531	tNET	RR	1	R13C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_d2_s0/CLK
21.840	-0.278	tSu		1	R13C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_d2_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.590, 84.397%; tC2Q: 0.294, 15.603%
Required Clock Path Delay	cell: 0.587, 27.713%; route: 1.531, 72.287%

Path23

Path Summary:

Slack	17.827
Data Arrival Time	4.022
Data Required Time	21.849
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.022	1.596	tNET	FF	1	R15C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.127	1.541	tNET	RR	1	R15C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLK
21.849	-0.278	tSu		1	R15C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3

Path Statistics:

Clock Skew	-0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.596, 84.449%; tC2Q: 0.294, 15.551%
Required Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%

Path24

Path Summary:

Slack	17.827
Data Arrival Time	4.024
Data Required Time	21.851
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.024	1.598	tNET	FF	1	R16C8[3][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.129	1.542	tNET	RR	1	R16C8[3][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3/CLK
21.851	-0.278	tSu		1	R16C8[3][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_7_s3

Path Statistics:

Clock Skew	-0.003
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.598, 84.461%; tC2Q: 0.294, 15.539%
Required Clock Path Delay	cell: 0.587, 27.570%; route: 1.542, 72.430%

Path25

Path Summary:

Slack	17.827
Data Arrival Time	4.022
Data Required Time	21.849
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
2.132	1.545	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
2.426	0.294	tC2Q	RF	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
4.022	1.596	tNET	FF	1	R15C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clkin
20.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
20.587	0.587	tINS	RR	185	IOB26[A]	clk_ibuf/O
22.127	1.541	tNET	RR	1	R15C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLK
21.849	-0.278	tSu		1	R15C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3

Path Statistics:

Clock Skew	-0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.587, 27.531%; route: 1.545, 72.469%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.596, 84.449%; tC2Q: 0.294, 15.551%
Required Clock Path Delay	cell: 0.587, 27.589%; route: 1.541, 72.411%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.989
Data Arrival Time	2.211
Data Required Time	1.222
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.211	0.785	tNET	RR	1	R11C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.275	0.694	tNET	RR	1	R11C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_3_s0/CLK
1.222	-0.053	tHld		1	R11C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_3_s0

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.785, 84.499%; tC2Q: 0.144, 15.501%
Required Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%

Path2

Path Summary:

Slack	0.989
Data Arrival Time	2.211
Data Required Time	1.222
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.211	0.785	tNET	RR	1	R11C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.275	0.694	tNET	RR	1	R11C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0/CLK
1.222	-0.053	tHld		1	R11C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_4_s0

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.785, 84.499%; tC2Q: 0.144, 15.501%
Required Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%

Path3

Path Summary:

Slack	0.989
Data Arrival Time	2.211
Data Required Time	1.222
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_5_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.211	0.785	tNET	RR	1	R11C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.275	0.694	tNET	RR	1	R11C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_5_s0/CLK
1.222	-0.053	tHld		1	R11C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_5_s0

Path Statistics:

Clock Skew	-0.007
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.785, 84.499%; tC2Q: 0.144, 15.501%
Required Clock Path Delay	cell: 0.581, 45.566%; route: 0.694, 54.434%

Path4

Path Summary:

Slack	0.993
Data Arrival Time	2.225
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.225	0.799	tNET	RR	1	R9C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R9C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_0_s0/CLK
1.232	-0.053	tHld		1	R9C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_0_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.799, 84.730%; tC2Q: 0.144, 15.270%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path5

Path Summary:

Slack	0.993
Data Arrival Time	2.225
Data Required Time	1.232
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.225	0.799	tNET	RR	1	R9C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.285	0.704	tNET	RR	1	R9C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_2_s0/CLK
1.232	-0.053	tHld		1	R9C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_2_s0

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.799, 84.730%; tC2Q: 0.144, 15.270%
Required Clock Path Delay	cell: 0.581, 45.211%; route: 0.704, 54.789%

Path6

Path Summary:

Slack	0.993
Data Arrival Time	2.230
Data Required Time	1.237
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_1_s2
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.230	0.804	tNET	RR	1	R8C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_1_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.290	0.709	tNET	RR	1	R8C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_1_s2/CLK
1.237	-0.053	tHld		1	R8C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_1_s2

Path Statistics:

Clock Skew	0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.804, 84.810%; tC2Q: 0.144, 15.190%
Required Clock Path Delay	cell: 0.581, 45.036%; route: 0.709, 54.964%

Path7

Path Summary:

Slack	0.995
Data Arrival Time	2.224
Data Required Time	1.229
From	u_reset_key/key_1_s0
To	led_cnt_6_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C5[2][A]	led_cnt_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R15C5[2][A]	led_cnt_6_s0/CLK
1.229	-0.053	tHld		1	R15C5[2][A]	led_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.317%; route: 0.701, 54.683%

Path8

Path Summary:

Slack	0.995
Data Arrival Time	2.224
Data Required Time	1.229
From	u_reset_key/key_1_s0
To	led_cnt_8_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C5[0][A]	led_cnt_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R15C5[0][A]	led_cnt_8_s0/CLK
1.229	-0.053	tHld		1	R15C5[0][A]	led_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.317%; route: 0.701, 54.683%

Path9

Path Summary:

Slack	0.995
Data Arrival Time	2.224
Data Required Time	1.229
From	u_reset_key/key_1_s0
To	led_cnt_19_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C5[1][B]	led_cnt_19_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R15C5[1][B]	led_cnt_19_s0/CLK
1.229	-0.053	tHld		1	R15C5[1][B]	led_cnt_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.317%; route: 0.701, 54.683%

Path10

Path Summary:

Slack	0.995
Data Arrival Time	2.224
Data Required Time	1.229
From	u_reset_key/key_1_s0
To	led_cnt_20_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C5[0][B]	led_cnt_20_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R15C5[0][B]	led_cnt_20_s0/CLK
1.229	-0.053	tHld		1	R15C5[0][B]	led_cnt_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.317%; route: 0.701, 54.683%

Path11

Path Summary:

Slack	0.996
Data Arrival Time	2.240
Data Required Time	1.244
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.240	0.814	tNET	RR	1	R6C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.297	0.716	tNET	RR	1	R6C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4/CLK
1.244	-0.053	tHld		1	R6C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/flag_0_s4

Path Statistics:

Clock Skew	0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.814, 84.969%; tC2Q: 0.144, 15.031%
Required Clock Path Delay	cell: 0.581, 44.801%; route: 0.716, 55.199%

Path12

Path Summary:

Slack	0.996
Data Arrival Time	2.240
Data Required Time	1.244
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.240	0.814	tNET	RR	1	R6C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.297	0.716	tNET	RR	1	R6C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_1_s0/CLK
1.244	-0.053	tHld		1	R6C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/cs_memsync_1_s0

Path Statistics:

Clock Skew	0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.814, 84.969%; tC2Q: 0.144, 15.031%
Required Clock Path Delay	cell: 0.581, 44.801%; route: 0.716, 55.199%

Path13

Path Summary:

Slack	0.996
Data Arrival Time	2.241
Data Required Time	1.245
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/count_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.241	0.816	tNET	RR	1	R5C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.298	0.718	tNET	RR	1	R5C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_0_s0/CLK
1.245	-0.053	tHld		1	R5C8[1][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_0_s0

Path Statistics:

Clock Skew	0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 84.996%; tC2Q: 0.144, 15.004%
Required Clock Path Delay	cell: 0.581, 44.741%; route: 0.718, 55.259%

Path14

Path Summary:

Slack	0.996
Data Arrival Time	2.241
Data Required Time	1.245
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/count_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.241	0.816	tNET	RR	1	R5C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.298	0.718	tNET	RR	1	R5C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_1_s0/CLK
1.245	-0.053	tHld		1	R5C8[1][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_1_s0

Path Statistics:

Clock Skew	0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 84.996%; tC2Q: 0.144, 15.004%
Required Clock Path Delay	cell: 0.581, 44.741%; route: 0.718, 55.259%

Path15

Path Summary:

Slack	0.996
Data Arrival Time	2.241
Data Required Time	1.245
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/count_2_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.241	0.816	tNET	RR	1	R5C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.298	0.718	tNET	RR	1	R5C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_2_s0/CLK
1.245	-0.053	tHld		1	R5C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/count_2_s0

Path Statistics:

Clock Skew	0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.816, 84.996%; tC2Q: 0.144, 15.004%
Required Clock Path Delay	cell: 0.581, 44.741%; route: 0.718, 55.259%

Path16

Path Summary:

Slack	0.996
Data Arrival Time	2.243
Data Required Time	1.247
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.243	0.817	tNET	RR	1	R4C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0/CLK
1.247	-0.053	tHld		1	R4C10[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/dll_rst_s0

Path Statistics:

Clock Skew	0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.817, 85.023%; tC2Q: 0.144, 14.977%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path17

Path Summary:

Slack	0.996
Data Arrival Time	2.243
Data Required Time	1.247
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.243	0.817	tNET	RR	1	R4C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0/CLK
1.247	-0.053	tHld		1	R4C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_syn_0_s0

Path Statistics:

Clock Skew	0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.817, 85.023%; tC2Q: 0.144, 14.977%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path18

Path Summary:

Slack	0.996
Data Arrival Time	2.243
Data Required Time	1.247
From	u_reset_key/key_1_s0
To	u_Gowin_PLL/u_pll_init/rEnable_1_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.243	0.817	tNET	RR	1	R4C6[1][A]	u_Gowin_PLL/u_pll_init/rEnable_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[1][A]	u_Gowin_PLL/u_pll_init/rEnable_1_s0/CLK
1.247	-0.053	tHld		1	R4C6[1][A]	u_Gowin_PLL/u_pll_init/rEnable_1_s0

Path Statistics:

Clock Skew	0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.817, 85.023%; tC2Q: 0.144, 14.977%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path19

Path Summary:

Slack	0.996
Data Arrival Time	2.243
Data Required Time	1.247
From	u_reset_key/key_1_s0
To	u_Gowin_PLL/u_pll_init/rEnable_0_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.243	0.817	tNET	RR	1	R4C6[1][B]	u_Gowin_PLL/u_pll_init/rEnable_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.300	0.719	tNET	RR	1	R4C6[1][B]	u_Gowin_PLL/u_pll_init/rEnable_0_s0/CLK
1.247	-0.053	tHld		1	R4C6[1][B]	u_Gowin_PLL/u_pll_init/rEnable_0_s0

Path Statistics:

Clock Skew	0.019
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.817, 85.023%; tC2Q: 0.144, 14.977%
Required Clock Path Delay	cell: 0.581, 44.681%; route: 0.719, 55.319%

Path20

Path Summary:

Slack	0.998
Data Arrival Time	2.223
Data Required Time	1.225
From	u_reset_key/key_1_s0
To	led_cnt_3_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.223	0.797	tNET	RR	1	R14C5[1][A]	led_cnt_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R14C5[1][A]	led_cnt_3_s0/CLK
1.225	-0.053	tHld		1	R14C5[1][A]	led_cnt_3_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.797, 84.697%; tC2Q: 0.144, 15.303%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path21

Path Summary:

Slack	0.998
Data Arrival Time	2.223
Data Required Time	1.225
From	u_reset_key/key_1_s0
To	led_cnt_4_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.223	0.797	tNET	RR	1	R14C5[1][B]	led_cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R14C5[1][B]	led_cnt_4_s0/CLK
1.225	-0.053	tHld		1	R14C5[1][B]	led_cnt_4_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.797, 84.697%; tC2Q: 0.144, 15.303%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path22

Path Summary:

Slack	0.998
Data Arrival Time	2.223
Data Required Time	1.225
From	u_reset_key/key_1_s0
To	led_cnt_13_s0
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.223	0.797	tNET	RR	1	R14C5[0][A]	led_cnt_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R14C5[0][A]	led_cnt_13_s0/CLK
1.225	-0.053	tHld		1	R14C5[0][A]	led_cnt_13_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.797, 84.697%; tC2Q: 0.144, 15.303%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path23

Path Summary:

Slack	0.999
Data Arrival Time	2.224
Data Required Time	1.225
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3/CLK
1.225	-0.053	tHld		1	R15C8[0][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_4_s3

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path24

Path Summary:

Slack	0.999
Data Arrival Time	2.224
Data Required Time	1.225
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3/CLK
1.225	-0.053	tHld		1	R15C8[0][B]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_13_s3

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Path25

Path Summary:

Slack	0.999
Data Arrival Time	2.224
Data Required Time	1.225
From	u_reset_key/key_1_s0
To	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1
Launch Clk	clkin:[R]
Latch Clk	clkin:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.282	0.701	tNET	RR	1	R18C8[3][A]	u_reset_key/key_1_s0/CLK
1.426	0.144	tC2Q	RR	569	R18C8[3][A]	u_reset_key/key_1_s0/Q
2.224	0.798	tNET	RR	1	R15C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkin
0.000	0.000	tCL	RR	1	IOB26[A]	clk_ibuf/I
0.581	0.581	tINS	RR	185	IOB26[A]	clk_ibuf/O
1.278	0.697	tNET	RR	1	R15C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1/CLK
1.225	-0.053	tHld		1	R15C8[2][A]	inst_apm64_top/u_apm64_top/u_apsram_sync/lock_cnt_5_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.581, 45.326%; route: 0.701, 54.674%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 84.717%; tC2Q: 0.144, 15.283%
Required Clock Path Delay	cell: 0.581, 45.459%; route: 0.697, 54.541%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKB

MPW2

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/mem0_mem0_0_1_s/CLKB

MPW4

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_0_s/CLKB

MPW6

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKA

MPW7

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_out_fifo/gowin_add_SDPX9B_mem2_mem2_0_1_s/CLKA

MPW8

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_0_s/CLKA

MPW9

MPW Summary:

Slack:	2.040
Actual Width:	2.902
Required Width:	0.862
Type:	Low Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
5.298	1.548	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
7.500	0.000			active clock edge time
7.500	0.000			userclk
7.500	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
8.200	0.700	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[1].u_apm64_data_lane/u_in_fifo/gowin_add_SDPB_mem0_mem0_0_1_s/CLKB

MPW10

MPW Summary:

Slack:	2.042
Actual Width:	2.904
Required Width:	0.862
Type:	High Pulse Width
Clock:	userclk
Objects:	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			userclk
0.000	0.000	tCL	RR	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
1.551	1.551	tNET	RR	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
3.750	0.000			active clock edge time
3.750	0.000			userclk
3.750	0.000	tCL	FF	inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT
4.455	0.705	tNET	FF	inst_apm64_top/u_apm64_top/u_apsram_wd/data_lane_gen[0].u_apm64_data_lane/u_out_fifo/mem2_mem2_0_1_s/CLKB

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2316	clk_x1	1.197	1.580
338	inst_apm64_top/u_apm64_top/init_calib_Z	1.197	2.117
185	clk_d	15.415	1.698
170	inst_apm64_top/u_apm64_top/config_done_Z	3.238	2.458
129	inst_apm64_top/u_apm64_top/rd_data_valid_d0	4.776	2.178
129	inst_apm64_top/u_apm64_top/u_apsram_wd/n89_6	3.030	1.991
96	inst_apm64_top/u_apm64_top/u_apsram_wd/n89_10	3.030	1.566
86	inst_apm64_top/u_apm64_top/c_state_data_lane[5]	3.534	2.253
65	inst_apm64_top/u_apm64_top/rd_data_valid_init[0]	5.509	1.208
65	inst_apm64_top/u_apm64_top/rd_data_valid_init[1]	4.784	1.984

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C13	100.00%
R2C36	100.00%
R2C37	100.00%
R2C41	100.00%
R2C43	100.00%
R2C44	100.00%
R3C81	100.00%
R6C65	100.00%
R12C68	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name mem_clk -period 1.875 -waveform {0 0.938} [get_nets {memory_clk}]
TC_CLOCK	Actived	create_clock -name clkin -period 20 -waveform {0 10} [get_ports {clk}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name userclk -source [get_nets {memory_clk}] -master_clock mem_clk -divide_by 4 -duty_cycle 50 [get_pins {inst_apm64_top/u_apm64_top/clk_x4_div/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clkin}] -group [get_clocks {mem_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -exclusive -group [get_clocks {userclk}] -group [get_clocks {mem_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -exclusive -group [get_clocks {clkin}] -group [get_clocks {userclk}]