Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\PSRAM_HS_2CH_V2\data\PSRAM_TOP.v
D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\ipcore\PSRAM_HS_2CH_V2\data\psram_code.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9MG100PC6/I5
Device GW1NR-9C
Created Time Wed Mar 10 14:16:41 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module PSRAM_Memory_Interface_HS_2CH_V2_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 55.531MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 55.531MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.199s, Peak memory usage = 55.531MB
    Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 55.531MB
    Optimizing Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.228s, Peak memory usage = 55.531MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 55.531MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 55.531MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 55.531MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 55.531MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 55.531MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 55.531MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 55.531MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 67.078MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.374s, Peak memory usage = 67.078MB
Generate output files:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 67.078MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 67.078MB

Resource

Resource Usage Summary

I/O Port 328
Emedded Port 52
I/O Buf 380
    IBUF 195
    OBUF 149
    IOBUF 36
Register 978
    DFF 2
    DFFP 4
    DFFPE 12
    DFFC 557
    DFFCE 403
LUT 1640
    LUT2 404
    LUT3 636
    LUT4 600
ALU 52
    ALU 52
INV 9
    INV 9
IOLOGIC 112
    IDES4 32
    OSER4 48
    IODELAY 32
BSRAM 4
    SDPX9B 4
CLOCK 3
    CLKDIV 1
    DHCEN 2

Resource Utilization Summary

Logic 1701(1649 LUTs, 52 ALUs) / 8640 20%
Register 978 / 6900 14%
  --Register as Latch 0 / 6900 0%
  --Register as FF 978 / 6900 14%
BSRAM 4 / 26 15%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 10.000 100.0 0.000 5.000 memory_clk_ibuf/I
memory_clk_p Base 10.000 100.0 0.000 5.000 memory_clk_p_ibuf/I
clk_d Base 10.000 100.0 0.000 5.000 clk_d_ibuf/I
clkdiv/CLKOUT.default_gen_clk Generated 20.000 50.0 0.000 10.000 memory_clk_ibuf/I memory_clk clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_d 100.0(MHz) 135.6(MHz) 5 TOP
2 clkdiv/CLKOUT.default_gen_clk 50.0(MHz) 138.1(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.623
Data Arrival Time 8.322
Data Required Time 10.945
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_13_s3
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.982 0.982 tINS RR 31 clk_d_ibuf/O
1.345 0.363 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
2.283 0.480 tNET FF 1 u_psram_sync/n47_s2/I1
3.382 1.099 tINS FF 4 u_psram_sync/n47_s2/F
3.862 0.480 tNET FF 1 u_psram_sync/n43_s2/I2
4.684 0.822 tINS FF 5 u_psram_sync/n43_s2/F
5.164 0.480 tNET FF 1 u_psram_sync/n38_s2/I1
6.263 1.099 tINS FF 3 u_psram_sync/n38_s2/F
6.743 0.480 tNET FF 1 u_psram_sync/n38_s5/I1
7.842 1.099 tINS FF 1 u_psram_sync/n38_s5/F
8.322 0.480 tNET FF 1 u_psram_sync/lock_cnt_13_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.982 0.982 tINS RR 31 clk_d_ibuf/O
11.345 0.363 tNET RR 1 u_psram_sync/lock_cnt_13_s3/CLK
10.945 -0.400 tSu 1 u_psram_sync/lock_cnt_13_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 2.623
Data Arrival Time 8.322
Data Required Time 10.945
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_14_s1
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.982 0.982 tINS RR 31 clk_d_ibuf/O
1.345 0.363 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
2.283 0.480 tNET FF 1 u_psram_sync/n47_s2/I1
3.382 1.099 tINS FF 4 u_psram_sync/n47_s2/F
3.862 0.480 tNET FF 1 u_psram_sync/n43_s2/I2
4.684 0.822 tINS FF 5 u_psram_sync/n43_s2/F
5.164 0.480 tNET FF 1 u_psram_sync/n38_s2/I1
6.263 1.099 tINS FF 3 u_psram_sync/n38_s2/F
6.743 0.480 tNET FF 1 u_psram_sync/n37_s1/I1
7.842 1.099 tINS FF 1 u_psram_sync/n37_s1/F
8.322 0.480 tNET FF 1 u_psram_sync/lock_cnt_14_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.982 0.982 tINS RR 31 clk_d_ibuf/O
11.345 0.363 tNET RR 1 u_psram_sync/lock_cnt_14_s1/CLK
10.945 -0.400 tSu 1 u_psram_sync/lock_cnt_14_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 2.886
Data Arrival Time 8.059
Data Required Time 10.945
From u_psram_sync/count_1_s0
To u_psram_sync/flag_0_s0
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.982 0.982 tINS RR 31 clk_d_ibuf/O
1.345 0.363 tNET RR 1 u_psram_sync/count_1_s0/CLK
1.803 0.458 tC2Q RF 6 u_psram_sync/count_1_s0/Q
2.283 0.480 tNET FF 1 u_psram_sync/n282_s14/I1
3.382 1.099 tINS FF 4 u_psram_sync/n282_s14/F
3.862 0.480 tNET FF 1 u_psram_sync/n348_s15/I1
4.961 1.099 tINS FF 1 u_psram_sync/n348_s15/F
5.441 0.480 tNET FF 1 u_psram_sync/n359_s9/I0
6.473 1.032 tINS FF 1 u_psram_sync/n359_s9/F
6.953 0.480 tNET FF 1 u_psram_sync/n359_s6/I3
7.579 0.626 tINS FF 1 u_psram_sync/n359_s6/F
8.059 0.480 tNET FF 1 u_psram_sync/flag_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.982 0.982 tINS RR 31 clk_d_ibuf/O
11.345 0.363 tNET RR 1 u_psram_sync/flag_0_s0/CLK
10.945 -0.400 tSu 1 u_psram_sync/flag_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.856, 57.429%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 2.900
Data Arrival Time 8.045
Data Required Time 10.945
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_11_s1
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.982 0.982 tINS RR 31 clk_d_ibuf/O
1.345 0.363 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
1.803 0.458 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
2.283 0.480 tNET FF 1 u_psram_sync/n47_s2/I1
3.382 1.099 tINS FF 4 u_psram_sync/n47_s2/F
3.862 0.480 tNET FF 1 u_psram_sync/n43_s2/I2
4.684 0.822 tINS FF 5 u_psram_sync/n43_s2/F
5.164 0.480 tNET FF 1 u_psram_sync/n41_s2/I2
5.986 0.822 tINS FF 2 u_psram_sync/n41_s2/F
6.466 0.480 tNET FF 1 u_psram_sync/n40_s1/I1
7.565 1.099 tINS FF 1 u_psram_sync/n40_s1/F
8.045 0.480 tNET FF 1 u_psram_sync/lock_cnt_11_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.982 0.982 tINS RR 31 clk_d_ibuf/O
11.345 0.363 tNET RR 1 u_psram_sync/lock_cnt_11_s1/CLK
10.945 -0.400 tSu 1 u_psram_sync/lock_cnt_11_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.842, 57.340%; route: 2.400, 35.819%; tC2Q: 0.458, 6.840%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 2.900
Data Arrival Time 8.045
Data Required Time 10.945
From u_psram_sync/cs_memsync_5_s0
To u_psram_sync/count_1_s0
Launch Clk clk_d[R]
Latch Clk clk_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_d
0.000 0.000 tCL RR 1 clk_d_ibuf/I
0.982 0.982 tINS RR 31 clk_d_ibuf/O
1.345 0.363 tNET RR 1 u_psram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 8 u_psram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_psram_sync/n348_s11/I1
3.382 1.099 tINS FF 4 u_psram_sync/n348_s11/F
3.862 0.480 tNET FF 1 u_psram_sync/n389_s3/I2
4.684 0.822 tINS FF 4 u_psram_sync/n389_s3/F
5.164 0.480 tNET FF 1 u_psram_sync/n388_s2/I1
6.263 1.099 tINS FF 2 u_psram_sync/n388_s2/F
6.743 0.480 tNET FF 1 u_psram_sync/n388_s1/I2
7.565 0.822 tINS FF 1 u_psram_sync/n388_s1/F
8.045 0.480 tNET FF 1 u_psram_sync/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_d
10.000 0.000 tCL RR 1 clk_d_ibuf/I
10.982 0.982 tINS RR 31 clk_d_ibuf/O
11.345 0.363 tNET RR 1 u_psram_sync/count_1_s0/CLK
10.945 -0.400 tSu 1 u_psram_sync/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.842, 57.340%; route: 2.400, 35.819%; tC2Q: 0.458, 6.840%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%