Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\datasheet\PROJECT\3_10\Gowin_PSRAM_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\gowin_rpll\gowin_rpll.v
D:\datasheet\PROJECT\3_10\Gowin_PSRAM_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram_memory_interface_hs_2ch_v2\psram_memory_interface_hs_2ch_v2.v
D:\datasheet\PROJECT\3_10\Gowin_PSRAM_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram_syn_top.v
D:\datasheet\PROJECT\3_10\Gowin_PSRAM_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram_test.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9C
Created Time Wed Mar 10 14:44:57 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module psram_syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.655s, Peak memory usage = 251.785MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 251.785MB
    Optimizing Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 251.785MB
    Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 251.785MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 251.785MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 251.785MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 251.785MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 251.785MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 251.785MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 251.785MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 251.785MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 251.785MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 251.785MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 251.785MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 251.785MB

Resource

Resource Usage Summary

I/O Port 6
Emedded Port 52
I/O Buf 58
    IBUF 2
    OBUF 20
    IOBUF 36
Register 1334
    DFF 2
    DFFP 6
    DFFPE 12
    DFFC 631
    DFFCE 683
LUT 2283
    LUT2 489
    LUT3 796
    LUT4 998
ALU 52
    ALU 52
INV 11
    INV 11
IOLOGIC 112
    IDES4 32
    OSER4 48
    IODELAY 32
BSRAM 4
    SDPX9B 4
CLOCK 4
    CLKDIV 1
    DHCEN 2
    rPLL 1

Resource Utilization Summary

Logic 2346(2294 LUTs, 52 ALUs) / 8640 27%
Register 1334 / 6900 19%
  --Register as Latch 0 / 6900 0%
  --Register as FF 1334 / 6900 19%
BSRAM 4 / 26 15%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
your_instance_name/rpll_inst/CLKOUT.default_gen_clk Generated 8.333 120.0 0.000 4.167 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUT
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Generated 8.333 120.0 2.083 6.250 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Generated 33.333 30.0 0.000 16.667 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Generated 25.000 40.0 0.000 12.500 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD3
u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk Generated 16.667 60.0 0.000 8.333 your_instance_name/rpll_inst/CLKOUT your_instance_name/rpll_inst/CLKOUT.default_gen_clk u_PSRAM_TOP/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk 30.0(MHz) 182.9(MHz) 5 TOP
2 u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk 60.0(MHz) 154.7(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.383
Data Arrival Time 2.224
Data Required Time 5.607
From u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0
To u_PSRAM_TOP/u_dhcen_clk_x2
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.259 1.259 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.528 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK
1.868 0.340 tC2Q RF 9 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q
2.224 0.356 tNET FF 1 u_PSRAM_TOP/u_dhcen_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
4.167 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
5.469 1.302 tCL FF 1 your_instance_name/rpll_inst/CLKOUT
5.825 0.356 tNET FF 3 u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN
5.795 -0.030 tUnc u_PSRAM_TOP/u_dhcen_clk_x2
5.607 -0.188 tSu 1 u_PSRAM_TOP/u_dhcen_clk_x2
Path Statistics:
Clock Skew: 0.130
Setup Relationship: 4.167
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.356, 100.000%

Path 2

Path Summary:
Slack 5.439
Data Arrival Time 2.224
Data Required Time 7.662
From u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0
To u_PSRAM_TOP/u_dhcen_clk_x2p
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUTP.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
1.259 1.259 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.528 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK
1.868 0.340 tC2Q RF 9 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q
2.224 0.356 tNET FF 1 u_PSRAM_TOP/u_dhcen_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
6.250 0.000 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk
7.525 1.275 tCL FF 1 your_instance_name/rpll_inst/CLKOUTP
7.880 0.356 tNET FF 3 u_PSRAM_TOP/u_dhcen_clk_x2p/CLKIN
7.850 -0.030 tUnc u_PSRAM_TOP/u_dhcen_clk_x2p
7.662 -0.188 tSu 1 u_PSRAM_TOP/u_dhcen_clk_x2p
Path Statistics:
Clock Skew: 0.102
Setup Relationship: 6.250
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.356, 100.000%

Path 3

Path Summary:
Slack 9.094
Data Arrival Time 1.234
Data Required Time 10.328
From u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk
0.269 0.269 tCL RR 1391 u_PSRAM_TOP/clkdiv/CLKOUT
0.538 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK
0.878 0.340 tC2Q RF 11 u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q
1.234 0.356 tNET FF 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.333 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
9.636 1.302 tCL RR 1 your_instance_name/rpll_inst/CLKOUT
9.905 0.269 tNET RR 3 u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN
10.089 0.184 tINS RR 73 u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT
10.358 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
10.328 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
10.328 0.000 tSu 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
Path Statistics:
Clock Skew: 1.486
Setup Relationship: 8.333
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.184, 25.476%; route: 0.538, 74.524%

Path 4

Path Summary:
Slack 9.094
Data Arrival Time 1.234
Data Required Time 10.328
From u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk
0.269 0.269 tCL RR 1391 u_PSRAM_TOP/clkdiv/CLKOUT
0.538 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK
0.878 0.340 tC2Q RF 11 u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q
1.234 0.356 tNET FF 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.333 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
9.636 1.302 tCL RR 1 your_instance_name/rpll_inst/CLKOUT
9.905 0.269 tNET RR 3 u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN
10.089 0.184 tINS RR 73 u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT
10.358 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
10.328 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
10.328 0.000 tSu 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
Path Statistics:
Clock Skew: 1.486
Setup Relationship: 8.333
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.184, 25.476%; route: 0.538, 74.524%

Path 5

Path Summary:
Slack 9.094
Data Arrival Time 1.234
Data Required Time 10.328
From u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk[R]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk
0.269 0.269 tCL RR 1391 u_PSRAM_TOP/clkdiv/CLKOUT
0.538 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/CLK
0.878 0.340 tC2Q RF 11 u_PSRAM_TOP/u_psram_top1/u_psram_init/calib_1_s0/Q
1.234 0.356 tNET FF 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
8.333 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
9.636 1.302 tCL RR 1 your_instance_name/rpll_inst/CLKOUT
9.905 0.269 tNET RR 3 u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN
10.089 0.184 tINS RR 73 u_PSRAM_TOP/u_dhcen_clk_x2/CLKOUT
10.358 0.269 tNET RR 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
10.328 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
10.328 0.000 tSu 1 u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
Path Statistics:
Clock Skew: 1.486
Setup Relationship: 8.333
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.269, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.356, 51.155%; tC2Q: 0.340, 48.845%
Required Clock Path Delay: cell: 0.184, 25.476%; route: 0.538, 74.524%