Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\gwide\49228\Gowin\Gowin_V1.9.7.02Beta\IDE\data\ipcores\gw_jtag.v
D:\datasheet\PROJECT\3_10\Gowin_PSRAM_Memory_Interface_HS_2CH_refDesign\GW1NR9-MG100\project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.02Beta
Part Number GW1NR-LV9MG100PC6/I5
Device GW1NR-9C
Created Time Wed Mar 10 09:48:45 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 41.309MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 41.309MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 41.309MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 41.309MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 41.309MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 41.309MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.309MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 41.309MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.309MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 41.309MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 41.309MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 41.309MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 56.004MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 56.004MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 56.004MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 56.004MB

Resource

Resource Usage Summary

I/O Port 69
I/O Buf 69
    IBUF 68
    OBUF 1
Register 483
    DFF 128
    DFFP 1
    DFFPE 33
    DFFC 28
    DFFCE 287
    DFFNP 2
    DFFNC 4
LUT 399
    LUT2 57
    LUT3 83
    LUT4 259
MUX 1
    MUX16 1
ALU 9
    ALU 9
INV 2
    INV 2
BSRAM 4
    SDPX9B 4

Resource Utilization Summary

Logic 418(409 LUTs, 9 ALUs) / 8640 5%
Register 483 / 6744 7%
  --Register as Latch 0 / 6744 0%
  --Register as FF 483 / 6744 7%
BSRAM 4 / 26 15%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_x1 Base 10.000 100.0 0.000 5.000 clk_x1_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 100.0(MHz) 136.8(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.690
Data Arrival Time 8.255
Data Required Time 10.945
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.982 0.982 tINS RR 185 clk_x1_ibuf/O
1.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.803 0.458 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
2.283 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/I0
3.315 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/F
3.795 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s7/I1
4.894 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.374 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s4/I1
6.473 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.953 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n472_s1/I2
7.775 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n472_s1/F
8.255 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.982 0.982 tINS RR 185 clk_x1_ibuf/O
11.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.945 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.052, 58.637%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 2.690
Data Arrival Time 8.255
Data Required Time 10.945
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.982 0.982 tINS RR 185 clk_x1_ibuf/O
1.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.803 0.458 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
2.283 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/I0
3.315 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/F
3.795 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s7/I1
4.894 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.374 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s4/I1
6.473 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.953 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n469_s1/I2
7.775 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n469_s1/F
8.255 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.982 0.982 tINS RR 185 clk_x1_ibuf/O
11.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.945 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.052, 58.637%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 2.690
Data Arrival Time 8.255
Data Required Time 10.945
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.982 0.982 tINS RR 185 clk_x1_ibuf/O
1.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.803 0.458 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
2.283 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/I0
3.315 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/F
3.795 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s7/I1
4.894 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.374 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s4/I1
6.473 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.953 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n467_s1/I2
7.775 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n467_s1/F
8.255 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.982 0.982 tINS RR 185 clk_x1_ibuf/O
11.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.945 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.052, 58.637%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 2.690
Data Arrival Time 8.255
Data Required Time 10.945
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.982 0.982 tINS RR 185 clk_x1_ibuf/O
1.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.803 0.458 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
2.283 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/I0
3.315 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/F
3.795 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s7/I1
4.894 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.374 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s4/I1
6.473 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.953 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n465_s1/I2
7.775 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n465_s1/F
8.255 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.982 0.982 tINS RR 185 clk_x1_ibuf/O
11.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.945 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.052, 58.637%; route: 2.400, 34.731%; tC2Q: 0.458, 6.633%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 2.886
Data Arrival Time 8.059
Data Required Time 10.945
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.982 0.982 tINS RR 185 clk_x1_ibuf/O
1.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.803 0.458 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
2.283 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/I0
3.315 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n464_s11/F
3.795 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s7/I1
4.894 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.374 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n464_s4/I1
6.473 1.099 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.953 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n471_s3/I3
7.579 0.626 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n471_s3/F
8.059 0.480 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_x1
10.000 0.000 tCL RR 1 clk_x1_ibuf/I
10.982 0.982 tINS RR 185 clk_x1_ibuf/O
11.345 0.363 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.945 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.856, 57.429%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%