Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\impl\gwsynthesis\MIPI_RefDesign.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\mipi.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\mipi.sdc
Tool Version	V1.9.12 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Tue Aug 26 16:34:39 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	3489
Numbers of Endpoints Analyzed	4283
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	sys_clk	Base	20.000	50.000	0.000	10.000			clkx2x4
2	sclk_tx	Base	100.000	10.000	0.000	50.000			sclk_tx
3	clk_byte_out	Base	20.000	50.000	0.000	10.000			clk_byte_out
4	HS_CLK_RX_P	Base	10.000	100.000	0.000	5.000			HS_CLK_RX_P GND
5	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i
6	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Generated	12.500	80.000	0.000	6.250	clkx2x4_ibuf/I	sys_clk	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1
7	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3.default_gen_clk	Generated	12.500	80.000	0.000	6.250	clkx2x4_ibuf/I	sys_clk	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	sys_clk	50.000(MHz)	168.049(MHz)	7	TOP
2	sclk_tx	10.000(MHz)	337.801(MHz)	1	TOP
3	clk_byte_out	50.000(MHz)	153.905(MHz)	5	TOP
4	tck_pad_i	20.000(MHz)	97.412(MHz)	6	TOP

No timing paths to get frequency of HS_CLK_RX_P!

No timing paths to get frequency of Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1.default_gen_clk!

No timing paths to get frequency of Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
sys_clk	Setup	0.000	0
sys_clk	Hold	0.000	0
sclk_tx	Setup	0.000	0
sclk_tx	Hold	0.000	0
clk_byte_out	Setup	0.000	0
clk_byte_out	Hold	0.000	0
HS_CLK_RX_P	Setup	0.000	0
HS_CLK_RX_P	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Setup	0.000	0
Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Hold	0.000	0
Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3.default_gen_clk	Setup	0.000	0
Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	13.503	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.000	6.186
2	13.531	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_5_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.000	6.158
3	13.536	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_13_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.009	6.144
4	13.753	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_15_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	-0.002	5.938
5	13.765	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/Q0	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.010	5.914
6	13.809	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.011	5.869
7	13.858	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_14_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.009	5.821
8	13.924	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_8_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.002	5.762
9	13.996	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/dout_6_s0/D	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.041	5.900
10	14.041	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_10_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.002	5.646
11	14.049	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0/Q	Gowin_PLL_inst/u_pll_init/rInitFsmC_2_s0/D	sys_clk:[R]	sys_clk:[R]	20.000	0.041	5.846
12	14.054	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.029	5.606
13	14.056	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_9_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.021	5.612
14	14.079	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_12_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.011	5.599
15	14.122	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_0_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	-0.031	5.598
16	14.209	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.005	5.475
17	14.209	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_0_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.007	5.473
18	14.219	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	-0.038	5.508
19	14.271	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_7_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.002	5.416
20	14.379	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0/Q	Gowin_PLL_inst/u_pll_init/rInitFsmC_1_s0/D	sys_clk:[R]	sys_clk:[R]	20.000	0.041	5.516
21	14.393	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.019	5.276
22	14.417	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_11_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.007	5.265
23	14.439	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.019	5.230
24	14.535	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.029	5.125
25	14.564	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	20.000	0.029	5.096

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.148	gw_gao_inst_0/u_la0_top/expression0_addr_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/ADA[0]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	-0.010	0.195
2	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	0.235
3	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	0.235
4	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	0.235
5	0.205	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.005	0.237
6	0.205	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.005	0.237
7	0.206	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.005	0.238
8	0.206	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.005	0.238
9	0.219	Gowin_PLL_inst/u_pll_init/rRomAddr_1_s1/Q	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/AD[6]	sys_clk:[R]	sys_clk:[R]	0.000	-0.014	0.270
10	0.229	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[3]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.003	0.269
11	0.235	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[8]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.017	0.255
12	0.241	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[8]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.021	0.257
13	0.245	gw_gao_inst_0/u_la0_top/expression0_data_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	-0.002	0.284
14	0.250	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/ADB[0]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.014	0.299
15	0.253	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.005	0.285
16	0.254	Gowin_PLL_inst/u_pll_init/rRomAddr_0_s1/Q	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/AD[5]	sys_clk:[R]	sys_clk:[R]	0.000	-0.014	0.305
17	0.260	Gowin_PLL_inst/u_pll_init/rRomAddr_5_s1/Q	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/AD[10]	sys_clk:[R]	sys_clk:[R]	0.000	-0.010	0.305
18	0.261	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.001	0.299
19	0.261	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.001	0.299
20	0.275	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6/Q	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
21	0.275	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_10_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
22	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
23	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
24	0.275	gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_4_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
25	0.275	gw_gao_inst_0/u_la0_top/word_count_3_s0/Q	gw_gao_inst_0/u_la0_top/word_count_3_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.374	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.014	2.265
2	7.548	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.023	2.081
3	7.548	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.023	2.081
4	7.548	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.023	2.081
5	7.548	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.023	2.081
6	7.743	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.029	1.880
7	8.005	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.010	1.658
8	8.123	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	0.026	1.504
9	8.375	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.013	1.290
10	8.375	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.013	1.290
11	8.408	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.003	1.247
12	8.408	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.003	1.247
13	8.424	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.010	1.239
14	8.481	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.001	1.173
15	8.481	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.001	1.173
16	8.481	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.001	1.173
17	8.577	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.013	1.089
18	8.577	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.013	1.089
19	8.577	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.013	1.089
20	8.577	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.013	1.089
21	8.586	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.022	1.089
22	8.586	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.022	1.089
23	8.630	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.010	1.033
24	8.724	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.010	0.939
25	8.724	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	10.000	-0.010	0.939

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.299	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.004	0.242
2	10.397	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.348
3	10.397	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.348
4	10.397	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.348
5	10.397	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.348
6	10.397	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.348
7	10.397	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.348
8	10.401	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.348
9	10.401	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.348
10	10.401	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.348
11	10.401	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.348
12	10.416	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.367
13	10.416	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	-0.004	0.367
14	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
15	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
16	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
17	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
18	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
19	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
20	10.420	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.367
21	10.439	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.386
22	10.439	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.386
23	10.439	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.386
24	10.439	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.000	0.386
25	10.443	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	-10.000	0.004	0.386

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.493	3.743	0.250	Low Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
2	3.493	3.743	0.250	Low Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
3	3.493	3.743	0.250	Low Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
4	3.493	3.743	0.250	Low Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
5	3.503	3.753	0.250	High Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
6	3.503	3.753	0.250	High Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
7	3.503	3.753	0.250	High Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
8	3.503	3.753	0.250	High Pulse Width	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
9	7.753	8.753	1.000	Low Pulse Width	sys_clk	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4
10	7.763	8.763	1.000	High Pulse Width	sys_clk	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	13.503
Data Arrival Time	8.121
Data Required Time	21.623
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.268	0.526	tNET	RR	1	R16C39[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n854_s1/I2
6.729	0.461	tINS	RR	1	R16C39[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n854_s1/F
6.867	0.137	tNET	RR	1	R16C39[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n854_s0/I0
7.393	0.526	tINS	RR	1	R16C39[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n854_s0/F
8.121	0.728	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
21.623	-0.311	tSu		1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.965, 31.764%; route: 3.839, 62.053%; tC2Q: 0.382, 6.183%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%

Path2

Path Summary:

Slack	13.531
Data Arrival Time	8.092
Data Required Time	21.623
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_5_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.403	0.661	tNET	RR	1	R16C39[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n848_s1/I2
6.864	0.461	tINS	RR	1	R16C39[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n848_s1/F
6.867	0.003	tNET	RR	1	R16C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n848_s0/I0
7.364	0.498	tINS	RR	1	R16C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n848_s0/F
8.092	0.728	tNET	RR	1	R16C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.934	1.934	tNET	RR	1	R16C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_5_s0/CLK
21.623	-0.311	tSu		1	R16C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.936, 31.445%; route: 3.839, 62.343%; tC2Q: 0.382, 6.212%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%

Path3

Path Summary:

Slack	13.536
Data Arrival Time	8.078
Data Required Time	21.614
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.493	0.751	tNET	RR	1	R16C38[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n856_s1/I2
6.908	0.415	tINS	RR	1	R16C38[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n856_s1/F
6.911	0.003	tNET	RR	1	R16C38[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n856_s0/I0
7.326	0.415	tINS	RR	1	R16C38[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n856_s0/F
8.078	0.752	tNET	RR	1	R16C38[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.925	1.925	tNET	RR	1	R16C38[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_13_s0/CLK
21.614	-0.311	tSu		1	R16C38[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_13_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.807, 29.420%; route: 3.954, 64.354%; tC2Q: 0.382, 6.226%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.925, 100.000%

Path4

Path Summary:

Slack	13.753
Data Arrival Time	7.872
Data Required Time	21.625
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_15_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
7.008	1.266	tNET	RR	1	R17C35[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n858_s1/I2
7.271	0.262	tINS	RR	1	R17C35[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n858_s1/F
7.273	0.003	tNET	RR	1	R17C35[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n858_s0/I0
7.734	0.461	tINS	RR	1	R17C35[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n858_s0/F
7.872	0.137	tNET	RR	1	R17C35[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.936	1.936	tNET	RR	1	R17C35[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_15_s0/CLK
21.625	-0.311	tSu		1	R17C35[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_15_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.701, 28.653%; route: 3.854, 64.905%; tC2Q: 0.382, 6.442%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.936, 100.000%

Path5

Path Summary:

Slack	13.765
Data Arrival Time	7.860
Data Required Time	21.625
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.946	1.946	tNET	RR	16	IOL5[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/PCLK
2.581	0.635	tC2Q	RR	5	IOL5[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/Q0
5.515	2.934	tNET	RR	1	R9C54[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s2/I0
6.031	0.516	tINS	RR	1	R9C54[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s2/F
6.169	0.137	tNET	RR	1	R9C54[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s1/I3
6.690	0.521	tINS	RR	1	R9C54[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s1/F
6.693	0.003	tNET	RR	1	R9C54[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s0/I0
7.108	0.415	tINS	RR	1	R9C54[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s0/F
7.860	0.752	tNET	RR	1	R9C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.936	1.936	tNET	RR	1	R9C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0/CLK
21.625	-0.311	tSu		1	R9C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0

Path Statistics:

Clock Skew	-0.010
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.946, 100.000%
Arrival Data Path Delay	cell: 1.452, 24.561%; route: 3.826, 64.701%; tC2Q: 0.635, 10.738%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.936, 100.000%

Path6

Path Summary:

Slack	13.809
Data Arrival Time	7.803
Data Required Time	21.612
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.686	0.944	tNET	RR	1	R15C38[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n849_s1/I2
7.147	0.461	tINS	RR	1	R15C38[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n849_s1/F
7.149	0.003	tNET	RR	1	R15C38[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n849_s0/I0
7.666	0.516	tINS	RR	1	R15C38[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n849_s0/F
7.803	0.137	tNET	RR	1	R15C38[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.923	1.923	tNET	RR	1	R15C38[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0/CLK
21.612	-0.311	tSu		1	R15C38[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.955, 33.312%; route: 3.531, 60.170%; tC2Q: 0.382, 6.518%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.923, 100.000%

Path7

Path Summary:

Slack	13.858
Data Arrival Time	7.756
Data Required Time	21.614
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_14_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.493	0.751	tNET	RR	1	R16C38[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n857_s1/I2
6.954	0.461	tINS	RR	1	R16C38[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n857_s1/F
7.092	0.137	tNET	RR	1	R16C38[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n857_s0/I0
7.618	0.526	tINS	RR	1	R16C38[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n857_s0/F
7.756	0.137	tNET	RR	1	R16C38[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.925	1.925	tNET	RR	1	R16C38[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_14_s0/CLK
21.614	-0.311	tSu		1	R16C38[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_14_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.965, 33.756%; route: 3.474, 59.674%; tC2Q: 0.382, 6.571%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.925, 100.000%

Path8

Path Summary:

Slack	13.924
Data Arrival Time	7.697
Data Required Time	21.621
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_8_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.598	0.856	tNET	RR	1	R15C39[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n851_s1/I2
7.059	0.461	tINS	RR	1	R15C39[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n851_s1/F
7.062	0.003	tNET	RR	1	R15C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n851_s0/I0
7.559	0.498	tINS	RR	1	R15C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n851_s0/F
7.697	0.137	tNET	RR	1	R15C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.933	1.933	tNET	RR	1	R15C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_8_s0/CLK
21.621	-0.311	tSu		1	R15C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_8_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.936, 33.601%; route: 3.444, 59.761%; tC2Q: 0.382, 6.638%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.933, 100.000%

Path9

Path Summary:

Slack	13.996
Data Arrival Time	7.868
Data Required Time	21.863
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/dout_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.967	1.967	tNET	RR	1	R22C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_4_s0/CLK
2.350	0.382	tC2Q	RR	26	R22C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_4_s0/Q
4.239	1.889	tNET	RR	1	R15C33[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s2/I1
4.700	0.461	tINS	RR	24	R15C33[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s2/F
6.029	1.329	tNET	RR	1	R17C38[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n723_s8/I2
6.490	0.461	tINS	RR	1	R17C38[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n723_s8/F
6.492	0.003	tNET	RR	1	R17C38[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n723_s1/I3
7.014	0.521	tINS	RR	1	R17C38[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n723_s1/F
7.341	0.327	tNET	RR	1	R17C40[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n723_s0/I0
7.867	0.526	tINS	RR	1	R17C40[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n723_s0/F
7.867	0.000	tNET	RR	1	R17C40[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/dout_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.927	1.927	tNET	RR	1	R17C40[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/dout_6_s0/CLK
21.863	-0.064	tSu		1	R17C40[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/dout_6_s0

Path Statistics:

Clock Skew	-0.041
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.967, 100.000%
Arrival Data Path Delay	cell: 1.970, 33.390%; route: 3.548, 60.127%; tC2Q: 0.382, 6.483%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.927, 100.000%

Path10

Path Summary:

Slack	14.041
Data Arrival Time	7.581
Data Required Time	21.621
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_10_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.463	0.721	tNET	RR	1	R15C39[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n853_s1/I2
6.924	0.461	tINS	RR	1	R15C39[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n853_s1/F
6.927	0.003	tNET	RR	1	R15C39[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n853_s0/I0
7.443	0.516	tINS	RR	1	R15C39[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n853_s0/F
7.581	0.137	tNET	RR	1	R15C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.933	1.933	tNET	RR	1	R15C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_10_s0/CLK
21.621	-0.311	tSu		1	R15C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_10_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.955, 34.625%; route: 3.309, 58.601%; tC2Q: 0.382, 6.774%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.933, 100.000%

Path11

Path Summary:

Slack	14.049
Data Arrival Time	8.494
Data Required Time	22.543
From	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0
To	Gowin_PLL_inst/u_pll_init/rInitFsmC_2_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
2.648	1.965	tNET	RR	1	R24C37[1][A]	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0/CLK
3.015	0.368	tC2Q	RF	8	R24C37[1][A]	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0/Q
4.781	1.766	tNET	FF	2	R24C33[0][A]	Gowin_PLL_inst/u_pll_init/n4298_s19/CIN
4.831	0.050	tINS	FR	1	R24C33[0][A]	Gowin_PLL_inst/u_pll_init/n4298_s19/COUT
4.831	0.000	tNET	RR	2	R24C33[0][B]	Gowin_PLL_inst/u_pll_init/n4298_s20/CIN
4.881	0.050	tINS	RR	1	R24C33[0][B]	Gowin_PLL_inst/u_pll_init/n4298_s20/COUT
4.881	0.000	tNET	RR	2	R24C33[1][A]	Gowin_PLL_inst/u_pll_init/n4298_s21/CIN
4.931	0.050	tINS	RR	1	R24C33[1][A]	Gowin_PLL_inst/u_pll_init/n4298_s21/COUT
4.931	0.000	tNET	RR	2	R24C33[1][B]	Gowin_PLL_inst/u_pll_init/n4298_s22/CIN
4.981	0.050	tINS	RR	1	R24C33[1][B]	Gowin_PLL_inst/u_pll_init/n4298_s22/COUT
4.981	0.000	tNET	RR	2	R24C33[2][A]	Gowin_PLL_inst/u_pll_init/n4298_s23/CIN
5.031	0.050	tINS	RR	1	R24C33[2][A]	Gowin_PLL_inst/u_pll_init/n4298_s23/COUT
5.433	0.401	tNET	RR	1	R24C34[1][B]	Gowin_PLL_inst/u_pll_init/n4346_s4/I0
5.894	0.461	tINS	RR	4	R24C34[1][B]	Gowin_PLL_inst/u_pll_init/n4346_s4/F
6.664	0.770	tNET	RR	1	R27C36[3][A]	Gowin_PLL_inst/u_pll_init/n4328_s26/I0
7.185	0.521	tINS	RR	1	R27C36[3][A]	Gowin_PLL_inst/u_pll_init/n4328_s26/F
7.569	0.384	tNET	RR	1	R29C38[2][A]	Gowin_PLL_inst/u_pll_init/n4328_s25/I0
8.030	0.461	tINS	RR	1	R29C38[2][A]	Gowin_PLL_inst/u_pll_init/n4328_s25/F
8.033	0.003	tNET	RR	1	R29C38[1][B]	Gowin_PLL_inst/u_pll_init/n4328_s27/I3
8.494	0.461	tINS	RR	1	R29C38[1][B]	Gowin_PLL_inst/u_pll_init/n4328_s27/F
8.494	0.000	tNET	RR	1	R29C38[1][B]	Gowin_PLL_inst/u_pll_init/rInitFsmC_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sys_clk
20.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
20.683	0.683	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
22.607	1.924	tNET	RR	1	R29C38[1][B]	Gowin_PLL_inst/u_pll_init/rInitFsmC_2_s0/CLK
22.543	-0.064	tSu		1	R29C38[1][B]	Gowin_PLL_inst/u_pll_init/rInitFsmC_2_s0

Path Statistics:

Clock Skew	-0.041
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay	cell: 2.155, 36.861%; route: 3.324, 56.853%; tC2Q: 0.368, 6.286%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path12

Path Summary:

Slack	14.054
Data Arrival Time	7.557
Data Required Time	21.611
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.412	0.813	tNET	RR	1	R11C54[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n849_s0/I3
6.909	0.498	tINS	RR	1	R11C54[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n849_s0/F
7.557	0.647	tNET	RR	1	R11C54[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.922	1.922	tNET	RR	1	R11C54[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CLK
21.611	-0.311	tSu		1	R11C54[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0

Path Statistics:

Clock Skew	-0.029
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.960, 34.961%; route: 3.264, 58.216%; tC2Q: 0.382, 6.823%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.922, 100.000%

Path13

Path Summary:

Slack	14.056
Data Arrival Time	7.547
Data Required Time	21.602
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_9_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.683	0.941	tNET	RR	1	R15C37[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n852_s1/I2
7.144	0.461	tINS	RR	1	R15C37[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n852_s1/F
7.147	0.003	tNET	RR	1	R15C37[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n852_s0/I0
7.409	0.262	tINS	RR	1	R15C37[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n852_s0/F
7.547	0.137	tNET	RR	1	R15C37[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.914	1.914	tNET	RR	1	R15C37[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_9_s0/CLK
21.602	-0.311	tSu		1	R15C37[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_9_s0

Path Statistics:

Clock Skew	-0.021
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.701, 30.312%; route: 3.529, 62.873%; tC2Q: 0.382, 6.815%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.914, 100.000%

Path14

Path Summary:

Slack	14.079
Data Arrival Time	7.533
Data Required Time	21.612
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_12_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.686	0.944	tNET	RR	1	R15C38[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n855_s1/I2
6.976	0.290	tINS	RF	1	R15C38[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n855_s1/F
6.981	0.005	tNET	FF	1	R15C38[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n855_s0/I0
7.396	0.415	tINS	FR	1	R15C38[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n855_s0/F
7.533	0.137	tNET	RR	1	R15C38[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.923	1.923	tNET	RR	1	R15C38[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_12_s0/CLK
21.612	-0.311	tSu		1	R15C38[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_12_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.682, 30.051%; route: 3.534, 63.117%; tC2Q: 0.382, 6.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.923, 100.000%

Path15

Path Summary:

Slack	14.122
Data Arrival Time	7.532
Data Required Time	21.654
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_0_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.094	0.352	tNET	RR	1	R23C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n843_s1/I2
6.384	0.290	tINS	RF	1	R23C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n843_s1/F
6.389	0.005	tNET	FF	1	R23C39[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n843_s0/I0
6.804	0.415	tINS	FR	1	R23C39[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n843_s0/F
7.532	0.728	tNET	RR	1	R23C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.965	1.965	tNET	RR	1	R23C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_0_s0/CLK
21.654	-0.311	tSu		1	R23C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_0_s0

Path Statistics:

Clock Skew	0.031
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.682, 30.058%; route: 3.533, 63.109%; tC2Q: 0.382, 6.833%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.965, 100.000%

Path16

Path Summary:

Slack	14.209
Data Arrival Time	7.426
Data Required Time	21.634
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.791	1.191	tNET	RR	1	R9C55[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n846_s0/I3
7.288	0.498	tINS	RR	1	R9C55[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n846_s0/F
7.426	0.137	tNET	RR	1	R9C55[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.946	1.946	tNET	RR	1	R9C55[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0/CLK
21.634	-0.311	tSu		1	R9C55[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_3_s0

Path Statistics:

Clock Skew	-0.005
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.960, 35.799%; route: 3.133, 57.215%; tC2Q: 0.382, 6.986%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.946, 100.000%

Path17

Path Summary:

Slack	14.209
Data Arrival Time	7.423
Data Required Time	21.632
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_0_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.656	1.056	tNET	RR	1	R8C55[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n843_s0/I3
7.071	0.415	tINS	RR	1	R8C55[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n843_s0/F
7.423	0.352	tNET	RR	1	R8C56[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.943	1.943	tNET	RR	1	R8C56[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_0_s0/CLK
21.632	-0.311	tSu		1	R8C56[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_0_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.877, 34.308%; route: 3.213, 58.703%; tC2Q: 0.382, 6.989%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.943, 100.000%

Path18

Path Summary:

Slack	14.219
Data Arrival Time	7.442
Data Required Time	21.661
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
5.904	0.162	tNET	RR	1	R20C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n846_s1/I2
6.402	0.498	tINS	RR	1	R20C39[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n846_s1/F
6.404	0.003	tNET	RR	1	R20C39[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n846_s0/I0
6.819	0.415	tINS	RR	1	R20C39[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n846_s0/F
7.442	0.623	tNET	RR	1	R20C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.972	1.972	tNET	RR	1	R20C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CLK
21.661	-0.311	tSu		1	R20C39[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0

Path Statistics:

Clock Skew	0.038
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.890, 34.317%; route: 3.235, 58.738%; tC2Q: 0.382, 6.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.972, 100.000%

Path19

Path Summary:

Slack	14.271
Data Arrival Time	7.351
Data Required Time	21.621
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_7_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.934	1.934	tNET	RR	1	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.317	0.382	tC2Q	RR	24	R16C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.654	1.337	tNET	RR	1	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/I0
4.116	0.461	tINS	RR	8	R15C33[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n717_s6/F
5.226	1.110	tNET	RR	1	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/I3
5.742	0.516	tINS	RR	16	R21C39[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s6/F
6.463	0.721	tNET	RR	1	R15C39[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n850_s1/I2
6.753	0.290	tINS	RF	1	R15C39[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n850_s1/F
6.896	0.142	tNET	FF	1	R15C38[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n850_s0/I0
7.158	0.262	tINS	FR	1	R15C38[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n850_s0/F
7.351	0.192	tNET	RR	1	R15C39[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.933	1.933	tNET	RR	1	R15C39[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_7_s0/CLK
21.621	-0.311	tSu		1	R15C39[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_7_s0

Path Statistics:

Clock Skew	-0.002
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.934, 100.000%
Arrival Data Path Delay	cell: 1.530, 28.248%; route: 3.504, 64.690%; tC2Q: 0.382, 7.062%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.933, 100.000%

Path20

Path Summary:

Slack	14.379
Data Arrival Time	8.164
Data Required Time	22.543
From	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0
To	Gowin_PLL_inst/u_pll_init/rInitFsmC_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
2.648	1.965	tNET	RR	1	R24C37[1][A]	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0/CLK
3.015	0.368	tC2Q	RF	8	R24C37[1][A]	Gowin_PLL_inst/u_pll_init/rMdAddr_0_s0/Q
4.781	1.766	tNET	FF	2	R24C33[0][A]	Gowin_PLL_inst/u_pll_init/n4298_s19/CIN
4.831	0.050	tINS	FR	1	R24C33[0][A]	Gowin_PLL_inst/u_pll_init/n4298_s19/COUT
4.831	0.000	tNET	RR	2	R24C33[0][B]	Gowin_PLL_inst/u_pll_init/n4298_s20/CIN
4.881	0.050	tINS	RR	1	R24C33[0][B]	Gowin_PLL_inst/u_pll_init/n4298_s20/COUT
4.881	0.000	tNET	RR	2	R24C33[1][A]	Gowin_PLL_inst/u_pll_init/n4298_s21/CIN
4.931	0.050	tINS	RR	1	R24C33[1][A]	Gowin_PLL_inst/u_pll_init/n4298_s21/COUT
4.931	0.000	tNET	RR	2	R24C33[1][B]	Gowin_PLL_inst/u_pll_init/n4298_s22/CIN
4.981	0.050	tINS	RR	1	R24C33[1][B]	Gowin_PLL_inst/u_pll_init/n4298_s22/COUT
4.981	0.000	tNET	RR	2	R24C33[2][A]	Gowin_PLL_inst/u_pll_init/n4298_s23/CIN
5.031	0.050	tINS	RR	1	R24C33[2][A]	Gowin_PLL_inst/u_pll_init/n4298_s23/COUT
5.433	0.401	tNET	RR	1	R24C34[1][B]	Gowin_PLL_inst/u_pll_init/n4346_s4/I0
5.894	0.461	tINS	RR	4	R24C34[1][B]	Gowin_PLL_inst/u_pll_init/n4346_s4/F
6.749	0.855	tNET	RR	1	R27C36[3][B]	Gowin_PLL_inst/u_pll_init/n4329_s23/I0
7.164	0.415	tINS	RR	1	R27C36[3][B]	Gowin_PLL_inst/u_pll_init/n4329_s23/F
7.703	0.539	tNET	RR	1	R29C38[1][A]	Gowin_PLL_inst/u_pll_init/n4329_s21/I1
8.164	0.461	tINS	RR	1	R29C38[1][A]	Gowin_PLL_inst/u_pll_init/n4329_s21/F
8.164	0.000	tNET	RR	1	R29C38[1][A]	Gowin_PLL_inst/u_pll_init/rInitFsmC_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					sys_clk
20.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
20.683	0.683	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
22.607	1.924	tNET	RR	1	R29C38[1][A]	Gowin_PLL_inst/u_pll_init/rInitFsmC_1_s0/CLK
22.543	-0.064	tSu		1	R29C38[1][A]	Gowin_PLL_inst/u_pll_init/rInitFsmC_1_s0

Path Statistics:

Clock Skew	-0.041
Setup Relationship	20.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.779%; route: 1.965, 74.221%
Arrival Data Path Delay	cell: 1.587, 28.779%; route: 3.561, 64.559%; tC2Q: 0.368, 6.662%
Required Clock Path Delay	cell: 0.683, 26.181%; route: 1.924, 73.819%

Path21

Path Summary:

Slack	14.393
Data Arrival Time	7.227
Data Required Time	21.620
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.628	1.029	tNET	RR	1	R11C55[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n848_s0/I3
7.089	0.461	tINS	RR	1	R11C55[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n848_s0/F
7.227	0.137	tNET	RR	1	R11C55[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.931	1.931	tNET	RR	1	R11C55[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLK
21.620	-0.311	tSu		1	R11C55[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.924, 36.461%; route: 2.970, 56.290%; tC2Q: 0.382, 7.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.931, 100.000%

Path22

Path Summary:

Slack	14.417
Data Arrival Time	7.216
Data Required Time	21.632
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_11_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.048	0.449	tNET	RR	1	R8C54[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n854_s0/I3
6.463	0.415	tINS	RR	1	R8C54[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n854_s0/F
7.216	0.752	tNET	RR	1	R8C54[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.943	1.943	tNET	RR	1	R8C54[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_11_s0/CLK
21.632	-0.311	tSu		1	R8C54[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_11_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.877, 35.660%; route: 3.005, 57.075%; tC2Q: 0.382, 7.265%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.943, 100.000%

Path23

Path Summary:

Slack	14.439
Data Arrival Time	7.181
Data Required Time	21.620
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.628	1.029	tNET	RR	1	R11C55[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n847_s0/I3
7.043	0.415	tINS	RR	1	R11C55[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n847_s0/F
7.181	0.137	tNET	RR	1	R11C55[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.931	1.931	tNET	RR	1	R11C55[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
21.620	-0.311	tSu		1	R11C55[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0

Path Statistics:

Clock Skew	-0.019
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.877, 35.899%; route: 2.970, 56.788%; tC2Q: 0.382, 7.314%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.931, 100.000%

Path24

Path Summary:

Slack	14.535
Data Arrival Time	7.076
Data Required Time	21.611
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.412	0.813	tNET	RR	1	R11C54[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n850_s0/I3
6.938	0.526	tINS	RR	1	R11C54[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n850_s0/F
7.076	0.137	tNET	RR	1	R11C54[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.922	1.922	tNET	RR	1	R11C54[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0/CLK
21.611	-0.311	tSu		1	R11C54[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0

Path Statistics:

Clock Skew	-0.029
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.989, 38.805%; route: 2.754, 53.732%; tC2Q: 0.382, 7.463%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.922, 100.000%

Path25

Path Summary:

Slack	14.564
Data Arrival Time	7.047
Data Required Time	21.611
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.951	1.951	tNET	RR	1	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/CLK
2.333	0.382	tC2Q	RR	12	R7C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg3_5_s0/Q
3.977	1.644	tNET	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/I2
4.392	0.415	tINS	RR	1	R8C48[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s16/F
4.549	0.157	tNET	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/I2
5.071	0.521	tINS	RR	1	R8C47[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s12/F
5.073	0.003	tNET	RR	1	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/I2
5.599	0.526	tINS	RR	16	R8C47[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s3/F
6.412	0.813	tNET	RR	1	R11C54[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s0/I3
6.909	0.498	tINS	RR	1	R11C54[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s0/F
7.047	0.137	tNET	RR	1	R11C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.922	1.922	tNET	RR	1	R11C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CLK
21.611	-0.311	tSu		1	R11C54[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0

Path Statistics:

Clock Skew	-0.029
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%
Arrival Data Path Delay	cell: 1.960, 38.460%; route: 2.754, 54.035%; tC2Q: 0.382, 7.506%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.922, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.148
Data Arrival Time	2.594
Data Required Time	2.446
From	gw_gao_inst_0/u_la0_top/expression0_addr_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.399	1.048	tNET	RR	1	R30C51[0][A]	gw_gao_inst_0/u_la0_top/expression0_addr_0_s0/CLK
2.540	0.141	tC2Q	RF	1	R30C51[0][A]	gw_gao_inst_0/u_la0_top/expression0_addr_0_s0/Q
2.594	0.054	tNET	FF	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/ADA[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.409	1.058	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA
2.446	0.037	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 56.315%; route: 1.048, 43.685%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.054, 27.692%; tC2Q: 0.141, 72.308%
Required Clock Path Delay	cell: 1.351, 56.081%; route: 1.058, 43.919%

Path2

Path Summary:

Slack	0.193
Data Arrival Time	0.926
Data Required Time	0.733
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.691	0.691	tNET	RR	1	R29C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/CLK
0.832	0.141	tC2Q	RF	1	R29C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_21_s0/Q
0.926	0.094	tNET	FF	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.691, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path3

Path Summary:

Slack	0.193
Data Arrival Time	0.922
Data Required Time	0.729
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.687	0.687	tNET	RR	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/CLK
0.828	0.141	tC2Q	RF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_17_s0/Q
0.922	0.094	tNET	FF	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.687, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path4

Path Summary:

Slack	0.193
Data Arrival Time	0.922
Data Required Time	0.729
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.687	0.687	tNET	RR	1	R29C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK
0.828	0.141	tC2Q	RF	1	R29C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q
0.922	0.094	tNET	FF	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.687, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path5

Path Summary:

Slack	0.205
Data Arrival Time	0.938
Data Required Time	0.733
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.701	0.701	tNET	RR	1	R27C44[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK
0.845	0.144	tC2Q	RR	1	R27C44[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q
0.938	0.093	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path6

Path Summary:

Slack	0.205
Data Arrival Time	0.934
Data Required Time	0.729
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.697	0.697	tNET	RR	1	R27C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
0.841	0.144	tC2Q	RR	1	R27C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
0.934	0.093	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path7

Path Summary:

Slack	0.206
Data Arrival Time	0.935
Data Required Time	0.729
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.697	0.697	tNET	RR	1	R27C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK
0.838	0.141	tC2Q	RF	1	R27C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q
0.935	0.097	tNET	FF	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path8

Path Summary:

Slack	0.206
Data Arrival Time	0.935
Data Required Time	0.729
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.697	0.697	tNET	RR	1	R27C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/CLK
0.838	0.141	tC2Q	RF	1	R27C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_15_s0/Q
0.935	0.097	tNET	FF	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.097, 40.756%; tC2Q: 0.141, 59.244%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path9

Path Summary:

Slack	0.219
Data Arrival Time	1.626
Data Required Time	1.408
From	Gowin_PLL_inst/u_pll_init/rRomAddr_1_s1
To	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
1.356	0.681	tNET	RR	1	R30C35[0][A]	Gowin_PLL_inst/u_pll_init/rRomAddr_1_s1/CLK
1.497	0.141	tC2Q	RF	5	R30C35[0][A]	Gowin_PLL_inst/u_pll_init/rRomAddr_1_s1/Q
1.626	0.129	tNET	FF	1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/AD[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK
1.408	0.037	tHld		1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.129, 47.778%; tC2Q: 0.141, 52.222%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path10

Path Summary:

Slack	0.229
Data Arrival Time	0.966
Data Required Time	0.737
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.697	0.697	tNET	RR	1	R27C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK
0.838	0.141	tC2Q	RF	1	R27C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q
0.966	0.128	tNET	FF	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
0.737	0.037	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.128, 47.584%; tC2Q: 0.141, 52.416%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path11

Path Summary:

Slack	0.235
Data Arrival Time	0.968
Data Required Time	0.733
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.857	0.144	tC2Q	RR	8	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
0.968	0.111	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/ADA[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.017
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.111, 43.529%; tC2Q: 0.144, 56.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path12

Path Summary:

Slack	0.241
Data Arrival Time	0.970
Data Required Time	0.729
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.857	0.144	tC2Q	RR	8	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
0.970	0.113	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.692	0.692	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.729	0.037	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.113, 43.969%; tC2Q: 0.144, 56.031%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.692, 100.000%

Path13

Path Summary:

Slack	0.245
Data Arrival Time	2.691
Data Required Time	2.446
From	gw_gao_inst_0/u_la0_top/expression0_data_s0
To	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.407	1.056	tNET	RR	1	R32C51[1][A]	gw_gao_inst_0/u_la0_top/expression0_data_s0/CLK
2.551	0.144	tC2Q	RR	1	R32C51[1][A]	gw_gao_inst_0/u_la0_top/expression0_data_s0/Q
2.691	0.140	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.409	1.058	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA
2.446	0.037	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 56.128%; route: 1.056, 43.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 1.351, 56.081%; route: 1.058, 43.919%

Path14

Path Summary:

Slack	0.250
Data Arrival Time	0.985
Data Required Time	0.735
From	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
To	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.686	0.686	tNET	RR	1	R30C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.827	0.141	tC2Q	RF	1	R30C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/Q
0.985	0.158	tNET	FF	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/ADB[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.700	0.700	tNET	RR	1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB
0.735	0.035	tHld		1	BSRAM_R28[15]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.686, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.700, 100.000%

Path15

Path Summary:

Slack	0.253
Data Arrival Time	0.986
Data Required Time	0.733
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.701	0.701	tNET	RR	1	R27C42[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK
0.845	0.144	tC2Q	RR	1	R27C42[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q
0.986	0.141	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.701, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 49.474%; tC2Q: 0.144, 50.526%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path16

Path Summary:

Slack	0.254
Data Arrival Time	1.661
Data Required Time	1.408
From	Gowin_PLL_inst/u_pll_init/rRomAddr_0_s1
To	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
1.356	0.681	tNET	RR	1	R30C35[0][B]	Gowin_PLL_inst/u_pll_init/rRomAddr_0_s1/CLK
1.497	0.141	tC2Q	RF	6	R30C35[0][B]	Gowin_PLL_inst/u_pll_init/rRomAddr_0_s1/Q
1.661	0.164	tNET	FF	1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/AD[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK
1.408	0.037	tHld		1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.164, 53.770%; tC2Q: 0.141, 46.230%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path17

Path Summary:

Slack	0.260
Data Arrival Time	1.666
Data Required Time	1.406
From	Gowin_PLL_inst/u_pll_init/rRomAddr_5_s1
To	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
1.361	0.685	tNET	RR	1	R31C35[0][A]	Gowin_PLL_inst/u_pll_init/rRomAddr_5_s1/CLK
1.502	0.141	tC2Q	RF	2	R31C35[0][A]	Gowin_PLL_inst/u_pll_init/rRomAddr_5_s1/Q
1.666	0.164	tNET	FF	1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/AD[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	1	IOB29[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	104	IOB29[A]	clkx2x4_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK
1.406	0.035	tHld		1	BSRAM_R28[10]	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.164, 53.770%; tC2Q: 0.141, 46.230%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path18

Path Summary:

Slack	0.261
Data Arrival Time	0.994
Data Required Time	0.733
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.695	0.695	tNET	RR	1	R29C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK
0.836	0.141	tC2Q	RF	1	R29C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q
0.994	0.158	tNET	FF	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path19

Path Summary:

Slack	0.261
Data Arrival Time	0.994
Data Required Time	0.733
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.695	0.695	tNET	RR	1	R29C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
0.836	0.141	tC2Q	RF	1	R29C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
0.994	0.158	tNET	FF	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.696	0.696	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.733	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.695, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.696, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	2.704
Data Required Time	2.429
From	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6
To	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.404	1.053	tNET	RR	1	R29C54[0][A]	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6/CLK
2.545	0.141	tC2Q	RF	2	R29C54[0][A]	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6/Q
2.551	0.006	tNET	FF	1	R29C54[0][A]	gw_gao_inst_0/u_la0_top/n1027_s4/I1
2.704	0.153	tINS	FF	1	R29C54[0][A]	gw_gao_inst_0/u_la0_top/n1027_s4/F
2.704	0.000	tNET	FF	1	R29C54[0][A]	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.404	1.053	tNET	RR	1	R29C54[0][A]	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6/CLK
2.429	0.025	tHld		1	R29C54[0][A]	gw_gao_inst_0/u_la0_top/data_out_shift_reg_32_s6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.198%; route: 1.053, 43.802%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 56.198%; route: 1.053, 43.802%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	2.715
Data Required Time	2.440
From	gw_gao_inst_0/u_la0_top/address_counter_10_s0
To	gw_gao_inst_0/u_la0_top/address_counter_10_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.414	1.064	tNET	RR	1	R32C45[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.556	0.141	tC2Q	RF	5	R32C45[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q
2.562	0.006	tNET	FF	1	R32C45[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/I2
2.714	0.153	tINS	FF	1	R32C45[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/F
2.714	0.000	tNET	FF	1	R32C45[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.414	1.064	tNET	RR	1	R32C45[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.440	0.025	tHld		1	R32C45[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.954%; route: 1.064, 44.046%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.954%; route: 1.064, 44.046%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	0.997
Data Required Time	0.722
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.697	0.697	tNET	RR	1	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0/CLK
0.838	0.141	tC2Q	RF	3	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0/Q
0.844	0.006	tNET	FF	1	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n134_s0/I3
0.997	0.153	tINS	FF	1	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n134_s0/F
0.997	0.000	tNET	FF	1	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.697	0.697	tNET	RR	1	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0/CLK
0.722	0.025	tHld		1	R17C54[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane1_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.697, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.013
Data Required Time	0.738
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
0.854	0.141	tC2Q	RF	2	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/Q
0.860	0.006	tNET	FF	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n275_s0/I2
1.013	0.153	tINS	FF	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n275_s0/F
1.013	0.000	tNET	FF	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
0.738	0.025	tHld		1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	2.699
Data Required Time	2.424
From	gw_gao_inst_0/u_la0_top/bit_count_4_s1
To	gw_gao_inst_0/u_la0_top/bit_count_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.399	1.048	tNET	RR	1	R30C55[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.540	0.141	tC2Q	RF	5	R30C55[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/Q
2.546	0.006	tNET	FF	1	R30C55[0][A]	gw_gao_inst_0/u_la0_top/n871_s2/I2
2.699	0.153	tINS	FF	1	R30C55[0][A]	gw_gao_inst_0/u_la0_top/n871_s2/F
2.699	0.000	tNET	FF	1	R30C55[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.399	1.048	tNET	RR	1	R30C55[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1/CLK
2.424	0.025	tHld		1	R30C55[0][A]	gw_gao_inst_0/u_la0_top/bit_count_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 56.315%; route: 1.048, 43.685%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 56.315%; route: 1.048, 43.685%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	2.723
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/word_count_3_s0
To	gw_gao_inst_0/u_la0_top/word_count_3_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.423	1.072	tNET	RR	1	R26C53[0][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK
2.564	0.141	tC2Q	RF	3	R26C53[0][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0/Q
2.570	0.006	tNET	FF	1	R26C53[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_3_s0/I2
2.723	0.153	tINS	FF	1	R26C53[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_3_s0/F
2.723	0.000	tNET	FF	1	R26C53[0][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	250	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.423	1.072	tNET	RR	1	R26C53[0][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0/CLK
2.448	0.025	tHld		1	R26C53[0][A]	gw_gao_inst_0/u_la0_top/word_count_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.757%; route: 1.072, 44.243%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.757%; route: 1.072, 44.243%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.374
Data Arrival Time	14.205
Data Required Time	21.579
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.205	1.823	tNET	FF	1	R32C51[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.927	1.927	tNET	RR	1	R32C51[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0/CLK
21.579	-0.347	tSu		1	R32C51[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_0_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.823, 80.464%; tC2Q: 0.442, 19.536%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.927, 100.000%

Path2

Path Summary:

Slack	7.548
Data Arrival Time	14.022
Data Required Time	21.570
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.022	1.639	tNET	FF	1	R32C50[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.917	1.917	tNET	RR	1	R32C50[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1/CLK
21.570	-0.347	tSu		1	R32C50[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.639, 78.739%; tC2Q: 0.442, 21.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.917, 100.000%

Path3

Path Summary:

Slack	7.548
Data Arrival Time	14.022
Data Required Time	21.570
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.022	1.639	tNET	FF	1	R32C50[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.917	1.917	tNET	RR	1	R32C50[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
21.570	-0.347	tSu		1	R32C50[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.639, 78.739%; tC2Q: 0.442, 21.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.917, 100.000%

Path4

Path Summary:

Slack	7.548
Data Arrival Time	14.022
Data Required Time	21.570
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.022	1.639	tNET	FF	1	R32C50[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.917	1.917	tNET	RR	1	R32C50[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
21.570	-0.347	tSu		1	R32C50[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.639, 78.739%; tC2Q: 0.442, 21.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.917, 100.000%

Path5

Path Summary:

Slack	7.548
Data Arrival Time	14.022
Data Required Time	21.570
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.022	1.639	tNET	FF	1	R32C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.917	1.917	tNET	RR	1	R32C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
21.570	-0.347	tSu		1	R32C50[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.639, 78.739%; tC2Q: 0.442, 21.261%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.917, 100.000%

Path6

Path Summary:

Slack	7.743
Data Arrival Time	13.820
Data Required Time	21.564
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.820	1.438	tNET	FF	1	R31C50[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.911	1.911	tNET	RR	1	R31C50[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
21.564	-0.347	tSu		1	R31C50[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.029
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.438, 76.463%; tC2Q: 0.442, 23.537%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.911, 100.000%

Path7

Path Summary:

Slack	8.005
Data Arrival Time	13.598
Data Required Time	21.603
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.598	1.215	tNET	FF	1	R25C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.951	1.951	tNET	RR	1	R25C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
21.603	-0.347	tSu		1	R25C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.215, 73.303%; tC2Q: 0.442, 26.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path8

Path Summary:

Slack	8.123
Data Arrival Time	13.444
Data Required Time	21.567
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.444	1.061	tNET	FF	1	R30C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.915	1.915	tNET	RR	1	R30C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
21.567	-0.347	tSu		1	R30C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.026
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.061, 70.574%; tC2Q: 0.442, 29.426%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.915, 100.000%

Path9

Path Summary:

Slack	8.375
Data Arrival Time	13.230
Data Required Time	21.606
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.230	0.848	tNET	FF	1	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.953	1.953	tNET	RR	1	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
21.606	-0.347	tSu		1	R24C42[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.848, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.953, 100.000%

Path10

Path Summary:

Slack	8.375
Data Arrival Time	13.230
Data Required Time	21.606
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.230	0.848	tNET	FF	1	R24C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.953	1.953	tNET	RR	1	R24C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
21.606	-0.347	tSu		1	R24C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.848, 65.698%; tC2Q: 0.442, 34.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.953, 100.000%

Path11

Path Summary:

Slack	8.408
Data Arrival Time	13.188
Data Required Time	21.596
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.188	0.805	tNET	FF	1	R26C44[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.943	1.943	tNET	RR	1	R26C44[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
21.596	-0.347	tSu		1	R26C44[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.943, 100.000%

Path12

Path Summary:

Slack	8.408
Data Arrival Time	13.188
Data Required Time	21.596
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.188	0.805	tNET	FF	1	R26C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.943	1.943	tNET	RR	1	R26C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
21.596	-0.347	tSu		1	R26C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	0.003
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 64.529%; tC2Q: 0.442, 35.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.943, 100.000%

Path13

Path Summary:

Slack	8.424
Data Arrival Time	13.179
Data Required Time	21.603
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.179	0.796	tNET	FF	1	R25C44[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.951	1.951	tNET	RR	1	R25C44[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
21.603	-0.347	tSu		1	R25C44[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.796, 64.279%; tC2Q: 0.442, 35.721%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path14

Path Summary:

Slack	8.481
Data Arrival Time	13.113
Data Required Time	21.594
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.113	0.730	tNET	FF	1	R25C45[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.941	1.941	tNET	RR	1	R25C45[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
21.594	-0.347	tSu		1	R25C45[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.730, 62.260%; tC2Q: 0.442, 37.740%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.941, 100.000%

Path15

Path Summary:

Slack	8.481
Data Arrival Time	13.113
Data Required Time	21.594
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.113	0.730	tNET	FF	1	R25C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.941	1.941	tNET	RR	1	R25C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
21.594	-0.347	tSu		1	R25C45[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.730, 62.260%; tC2Q: 0.442, 37.740%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.941, 100.000%

Path16

Path Summary:

Slack	8.481
Data Arrival Time	13.113
Data Required Time	21.594
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.113	0.730	tNET	FF	1	R25C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.941	1.941	tNET	RR	1	R25C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
21.594	-0.347	tSu		1	R25C45[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.730, 62.260%; tC2Q: 0.442, 37.740%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.941, 100.000%

Path17

Path Summary:

Slack	8.577
Data Arrival Time	13.029
Data Required Time	21.606
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.029	0.646	tNET	FF	1	R24C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.953	1.953	tNET	RR	1	R24C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
21.606	-0.347	tSu		1	R24C44[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.646, 59.357%; tC2Q: 0.442, 40.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.953, 100.000%

Path18

Path Summary:

Slack	8.577
Data Arrival Time	13.029
Data Required Time	21.606
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.029	0.646	tNET	FF	1	R24C44[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.953	1.953	tNET	RR	1	R24C44[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
21.606	-0.347	tSu		1	R24C44[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.646, 59.357%; tC2Q: 0.442, 40.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.953, 100.000%

Path19

Path Summary:

Slack	8.577
Data Arrival Time	13.029
Data Required Time	21.606
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.029	0.646	tNET	FF	1	R24C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.953	1.953	tNET	RR	1	R24C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
21.606	-0.347	tSu		1	R24C44[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.646, 59.357%; tC2Q: 0.442, 40.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.953, 100.000%

Path20

Path Summary:

Slack	8.577
Data Arrival Time	13.029
Data Required Time	21.606
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.029	0.646	tNET	FF	1	R24C44[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.953	1.953	tNET	RR	1	R24C44[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
21.606	-0.347	tSu		1	R24C44[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.013
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.646, 59.357%; tC2Q: 0.442, 40.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.953, 100.000%

Path21

Path Summary:

Slack	8.586
Data Arrival Time	13.029
Data Required Time	21.615
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.029	0.646	tNET	FF	1	R24C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.962	1.962	tNET	RR	1	R24C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
21.615	-0.347	tSu		1	R24C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew	0.022
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.646, 59.357%; tC2Q: 0.442, 40.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.962, 100.000%

Path22

Path Summary:

Slack	8.586
Data Arrival Time	13.029
Data Required Time	21.615
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.029	0.646	tNET	FF	1	R24C43[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.962	1.962	tNET	RR	1	R24C43[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
21.615	-0.347	tSu		1	R24C43[1][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	0.022
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.646, 59.357%; tC2Q: 0.442, 40.643%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.962, 100.000%

Path23

Path Summary:

Slack	8.630
Data Arrival Time	12.973
Data Required Time	21.603
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.973	0.590	tNET	FF	1	R25C50[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.951	1.951	tNET	RR	1	R25C50[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
21.603	-0.347	tSu		1	R25C50[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.590, 57.143%; tC2Q: 0.442, 42.857%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path24

Path Summary:

Slack	8.724
Data Arrival Time	12.879
Data Required Time	21.603
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.879	0.496	tNET	FF	1	R25C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.951	1.951	tNET	RR	1	R25C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
21.603	-0.347	tSu		1	R25C46[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.496, 52.863%; tC2Q: 0.442, 47.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Path25

Path Summary:

Slack	8.724
Data Arrival Time	12.879
Data Required Time	21.603
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.940	1.940	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
12.383	0.442	tC2Q	FF	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.879	0.496	tNET	FF	1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk_byte_out
20.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
21.951	1.951	tNET	RR	1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
21.603	-0.347	tSu		1	R25C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.940, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.496, 52.863%; tC2Q: 0.442, 47.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.951, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.299
Data Arrival Time	10.955
Data Required Time	0.656
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
10.955	0.084	tNET	RR	1	R24C49[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.709	0.709	tNET	RR	1	R24C49[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.656	-0.053	tHld		1	R24C49[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 34.711%; tC2Q: 0.158, 65.289%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Path2

Path Summary:

Slack	10.397
Data Arrival Time	11.061
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C47[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C47[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.664	-0.053	tHld		1	R24C47[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path3

Path Summary:

Slack	10.397
Data Arrival Time	11.061
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C47[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C47[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.664	-0.053	tHld		1	R24C47[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path4

Path Summary:

Slack	10.397
Data Arrival Time	11.061
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.664	-0.053	tHld		1	R24C47[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path5

Path Summary:

Slack	10.397
Data Arrival Time	11.061
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C47[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C47[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.664	-0.053	tHld		1	R24C47[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path6

Path Summary:

Slack	10.397
Data Arrival Time	11.061
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C47[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C47[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.664	-0.053	tHld		1	R24C47[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path7

Path Summary:

Slack	10.397
Data Arrival Time	11.061
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C47[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C47[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.664	-0.053	tHld		1	R24C47[3][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path8

Path Summary:

Slack	10.401
Data Arrival Time	11.061
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C48[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C48[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.660	-0.053	tHld		1	R24C48[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path9

Path Summary:

Slack	10.401
Data Arrival Time	11.061
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.660	-0.053	tHld		1	R24C48[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path10

Path Summary:

Slack	10.401
Data Arrival Time	11.061
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C48[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C48[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.660	-0.053	tHld		1	R24C48[0][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path11

Path Summary:

Slack	10.401
Data Arrival Time	11.061
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.061	0.190	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.660	-0.053	tHld		1	R24C48[0][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.190, 54.598%; tC2Q: 0.158, 45.402%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path12

Path Summary:

Slack	10.416
Data Arrival Time	11.080
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.664	-0.053	tHld		1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path13

Path Summary:

Slack	10.416
Data Arrival Time	11.080
Data Required Time	0.664
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.717	0.717	tNET	RR	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.664	-0.053	tHld		1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.717, 100.000%

Path14

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
0.660	-0.053	tHld		1	R24C50[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path15

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
0.660	-0.053	tHld		1	R24C50[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path16

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
0.660	-0.053	tHld		1	R24C50[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path17

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
0.660	-0.053	tHld		1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path18

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
0.660	-0.053	tHld		1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path19

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
0.660	-0.053	tHld		1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path20

Path Summary:

Slack	10.420
Data Arrival Time	11.080
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.080	0.209	tNET	RR	1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
0.660	-0.053	tHld		1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.209, 56.948%; tC2Q: 0.158, 43.052%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path21

Path Summary:

Slack	10.439
Data Arrival Time	11.099
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.099	0.228	tNET	RR	1	R24C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.660	-0.053	tHld		1	R24C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 59.067%; tC2Q: 0.158, 40.933%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path22

Path Summary:

Slack	10.439
Data Arrival Time	11.099
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.099	0.228	tNET	RR	1	R24C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.660	-0.053	tHld		1	R24C46[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 59.067%; tC2Q: 0.158, 40.933%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path23

Path Summary:

Slack	10.439
Data Arrival Time	11.099
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.099	0.228	tNET	RR	1	R24C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.660	-0.053	tHld		1	R24C46[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 59.067%; tC2Q: 0.158, 40.933%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path24

Path Summary:

Slack	10.439
Data Arrival Time	11.099
Data Required Time	0.660
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.099	0.228	tNET	RR	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.713	0.713	tNET	RR	1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
0.660	-0.053	tHld		1	R24C46[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	-0.000
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 59.067%; tC2Q: 0.158, 40.933%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%

Path25

Path Summary:

Slack	10.443
Data Arrival Time	11.099
Data Required Time	0.656
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk_byte_out
10.000	0.000	tCL	FF	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
10.713	0.713	tNET	FF	1	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
10.871	0.158	tC2Q	FR	57	R24C49[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.099	0.228	tNET	RR	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	939	LEFTSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.709	0.709	tNET	RR	1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.656	-0.053	tHld		1	R24C45[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.004
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.713, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.228, 59.067%; tC2Q: 0.158, 40.933%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.709, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.493
Actual Width:	3.743
Required Width:	0.250
Type:	Low Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.688	0.688	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.654	1.967	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			HS_CLK_RX_P
10.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.675	0.675	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.397	0.722	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

MPW2

MPW Summary:

Slack:	3.493
Actual Width:	3.743
Required Width:	0.250
Type:	Low Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.688	0.688	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.654	1.967	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			HS_CLK_RX_P
10.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.675	0.675	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.397	0.722	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

MPW3

MPW Summary:

Slack:	3.493
Actual Width:	3.743
Required Width:	0.250
Type:	Low Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.688	0.688	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.654	1.967	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			HS_CLK_RX_P
10.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.675	0.675	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.397	0.722	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

MPW4

MPW Summary:

Slack:	3.493
Actual Width:	3.743
Required Width:	0.250
Type:	Low Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.688	0.688	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
7.654	1.967	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			HS_CLK_RX_P
10.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.675	0.675	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.397	0.722	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

MPW5

MPW Summary:

Slack:	3.503
Actual Width:	3.753
Required Width:	0.250
Type:	High Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			HS_CLK_RX_P
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.650	1.967	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.677	0.678	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.403	0.726	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK

MPW6

MPW Summary:

Slack:	3.503
Actual Width:	3.753
Required Width:	0.250
Type:	High Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			HS_CLK_RX_P
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.650	1.967	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.677	0.678	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.403	0.726	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK

MPW7

MPW Summary:

Slack:	3.503
Actual Width:	3.753
Required Width:	0.250
Type:	High Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			HS_CLK_RX_P
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.650	1.967	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.677	0.678	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.403	0.726	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK

MPW8

MPW Summary:

Slack:	3.503
Actual Width:	3.753
Required Width:	0.250
Type:	High Pulse Width
Clock:	HS_CLK_RX_P
Objects:	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			HS_CLK_RX_P
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
2.650	1.967	tNET	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			HS_CLK_RX_P
5.000	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.677	0.678	tINS	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.403	0.726	tNET	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK

MPW9

MPW Summary:

Slack:	7.753
Actual Width:	8.753
Required Width:	1.000
Type:	Low Pulse Width
Clock:	sys_clk
Objects:	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sys_clk
10.000	0.000	tCL	FF	clkx2x4_ibuf/I
10.688	0.688	tINS	FF	clkx2x4_ibuf/O
12.618	1.930	tNET	FF	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			sys_clk
20.000	0.000	tCL	RR	clkx2x4_ibuf/I
20.676	0.675	tINS	RR	clkx2x4_ibuf/O
21.371	0.695	tNET	RR	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK

MPW10

MPW Summary:

Slack:	7.763
Actual Width:	8.763
Required Width:	1.000
Type:	High Pulse Width
Clock:	sys_clk
Objects:	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			sys_clk
0.000	0.000	tCL	RR	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	clkx2x4_ibuf/O
2.614	1.932	tNET	RR	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			sys_clk
10.000	0.000	tCL	FF	clkx2x4_ibuf/I
10.677	0.678	tINS	FF	clkx2x4_ibuf/O
11.377	0.700	tNET	FF	Gowin_PLL_inst/u_pll_init/rRomDReg_0_s4/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
939	clk_byte_out	13.502	1.975
250	gw_gao_inst_0/control0[0]	19.867	2.725
104	clkx2x4_d	14.049	2.088
78	ready_d	17.257	1.821
57	gw_gao_inst_0/u_la0_top/rst_ao	7.374	1.880
54	gw_gao_inst_0/u_la0_top/n20_3	46.261	1.919
44	gw_gao_inst_0/u_la0_top/module_state[1]	20.872	1.170
42	gw_gao_inst_0/u_la0_top/module_state[0]	20.722	1.120
41	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt[7]	15.489	2.120
35	gw_gao_inst_0/u_la0_top/n995_5	44.354	1.398

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C4	100.00%
R2C6	100.00%
R2C7	100.00%
R2C39	100.00%
R3C12	100.00%
R4C49	100.00%
R7C32	100.00%
R13C62	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name sys_clk -period 20 -waveform {0 10} [get_ports {clkx2x4}]
TC_CLOCK	Actived	create_clock -name sclk_tx -period 100 -waveform {0 50} [get_nets {sclk_tx}]
TC_CLOCK	Actived	create_clock -name clk_byte_out -period 20 -waveform {0 10} [get_nets {clk_byte_out}]
TC_CLOCK	Actived	create_clock -name HS_CLK_RX_P -period 10 -waveform {0 5} [get_ports {HS_CLK_RX_P}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {HS_CLK_RX_P}] -to [get_clocks {HS_CLK_RX_P}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {sys_clk}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {sclk_tx}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk_byte_out}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {HS_CLK_RX_P}]