Synthesis Messages

Report Title	GowinSynthesis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\DPHY_TOP.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\ROM549X17.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\gowin_pll\gowin_pll_mod.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\mipi_rx_advance\mipi_rx_advance.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\mipi_tx_advance\mipi_tx_advance.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\src\pll_init.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a25_LVDS\MIPI_RefDesign\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Tue Aug 26 16:30:04 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	DPHY_TOP
Synthesis Process	Running parser: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 0.811s, Peak memory usage = 310.328MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.474s, Peak memory usage = 310.328MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.175s, Peak memory usage = 310.328MB Optimizing Phase 2: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.419s, Peak memory usage = 310.328MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.184s, Peak memory usage = 310.328MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 310.328MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 310.328MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 310.328MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 310.328MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 310.328MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 310.328MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 329.066MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 329.398MB Generate output files: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 329.398MB
Total Time and Memory Usage	CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 329.398MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	29
I/O Buf	19
IBUF	4
OBUF	5
ELVDS_TBUF	5
ELVDS_IOBUF	5
Register	1301
DFFSE	1
DFFRE	102
DFFPE	37
DFFCE	1161
LUT	2094
LUT2	198
LUT3	350
LUT4	1546
MUX	1
MUX16	1
ALU	41
ALU	41
INV	14
INV	14
IOLOGIC	13
IDES16	4
OSER16	5
IODELAY	4
BSRAM	7
SDPB	1
SDPX9B	4
pROM	2
CLOCK	3
CLKDIV	1
DHCE	1
PLLA	1
Black Box	1
GW_JTAG	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	2157(2116 LUT, 41 ALU) / 23040	10%
Register	1301 / 23685	6%
--Register as Latch	0 / 23685	0%
--Register as FF	1301 / 23685	6%
BSRAM	7 / 56	13%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Object
1	clkx2x4	Base	20.000	50.000	10.000			clkx2x4_ibuf/I
2	HS_CLK_RX_P	Base	10.000	100.000	5.000			MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
3	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	Generated	100.000	10.000	50.000	clkx2x4_ibuf/I	clkx2x4	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT0
4	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1.default_gen_clk	Generated	12.500	80.000	6.250	clkx2x4_ibuf/I	clkx2x4	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT1
5	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3.default_gen_clk	Generated	12.500	80.000	6.250	clkx2x4_ibuf/I	clkx2x4	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT3
6	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk	Generated	80.000	12.500	40.000	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO	HS_CLK_RX_P	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clkx2x4	50.000(MHz)	171.380(MHz)	7	TOP
2	HS_CLK_RX_P	100.000(MHz)	278.435(MHz)	2	TOP
3	Gowin_PLL_inst/u_pll/PLLA_inst/CLKOUT0.default_gen_clk	10.000(MHz)	408.372(MHz)	1	TOP
4	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk	12.500(MHz)	213.961(MHz)	5	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	3.204
Data Arrival Time	2.651
Data Required Time	5.855
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN
Launch Clk	HS_CLK_RX_P[F]
Latch Clk	HS_CLK_RX_P[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				HS_CLK_RX_P
0.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.058	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
1.440	0.382	tC2Q	RR	2	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q
1.815	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I2
2.276	0.461	tINS	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F
2.651	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
5.000	0.000				HS_CLK_RX_P
5.000	0.000	tCL	FF	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
5.688	0.688	tINS	FF	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
6.037	0.350	tNET	FF	3	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.855	-0.182	tSu		1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN

Path Statistics:

Clock Skew:	-0.020
Setup Relationship:	5.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay:	cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 2

Path Summary:

Slack	8.095
Data Arrival Time	2.651
Data Required Time	10.746
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk	HS_CLK_RX_P[R]
Latch Clk	HS_CLK_RX_P[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				HS_CLK_RX_P
0.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.058	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.440	0.382	tC2Q	RR	2	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.815	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.276	0.461	tINS	RR	4	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.651	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				HS_CLK_RX_P
10.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.682	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.057	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
10.746	-0.311	tSu		1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay:	cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 3

Path Summary:

Slack	8.095
Data Arrival Time	2.651
Data Required Time	10.746
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk	HS_CLK_RX_P[R]
Latch Clk	HS_CLK_RX_P[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				HS_CLK_RX_P
0.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.058	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.440	0.382	tC2Q	RR	2	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.815	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.276	0.461	tINS	RR	4	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.651	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				HS_CLK_RX_P
10.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.682	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.057	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
10.746	-0.311	tSu		1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay:	cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 4

Path Summary:

Slack	8.095
Data Arrival Time	2.651
Data Required Time	10.746
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk	HS_CLK_RX_P[R]
Latch Clk	HS_CLK_RX_P[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				HS_CLK_RX_P
0.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.058	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.440	0.382	tC2Q	RR	2	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.815	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.276	0.461	tINS	RR	4	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.651	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				HS_CLK_RX_P
10.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.682	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.057	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
10.746	-0.311	tSu		1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay:	cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%

Path 5

Path Summary:

Slack	8.095
Data Arrival Time	2.651
Data Required Time	10.746
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk	HS_CLK_RX_P[R]
Latch Clk	HS_CLK_RX_P[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				HS_CLK_RX_P
0.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
0.683	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
1.058	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.440	0.382	tC2Q	RR	2	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q
1.815	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2
2.276	0.461	tINS	RR	4	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F
2.651	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
10.000	0.000				HS_CLK_RX_P
10.000	0.000	tCL	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/IO
10.682	0.683	tINS	RR	5	MIPI_RX_Advance_Top/DPHY_RX_INST/U0_IB/O
11.057	0.375	tNET	RR	1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
10.746	-0.311	tSu		1	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	10.000
Logic Level:	2
Arrival Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%
Arrival Data Path Delay:	cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000%
Required Clock Path Delay:	cell: 0.683, 64.539%; route: 0.375, 35.461%