Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\impl\gwsynthesis\MIPI_RefDesign.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\mipi_rx.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\mipi_rx.sdc
Tool Version	V1.9.12 (64-bit)
Part Number	GW5ART-LV15MG132PC1/I0
Device	GW5ART-15
Device Version	A
Created Time	Tue Aug 26 16:49:23 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C1/I0
Hold Delay Model	Fast 0.945V 85C C1/I0
Numbers of Paths Analyzed	5961
Numbers of Endpoints Analyzed	5651
Numbers of Falling Endpoints	14
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk_byte_out	Base	10.667	93.747	0.000	5.333			clk_byte_out
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i
3	MIPI_CLK_RX_P	Base	10.000	100.000	0.000	5.000			MIPI_CLK_RX_P
4	clkx2x4	Base	20.000	50.000	0.000	10.000			clkx2x4_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk_byte_out	93.747(MHz)	145.586(MHz)	6	TOP
2	tck_pad_i	20.000(MHz)	76.452(MHz)	6	TOP
3	clkx2x4	50.000(MHz)	165.135(MHz)	7	TOP

No timing paths to get frequency of MIPI_CLK_RX_P!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_byte_out	Setup	0.000	0
clk_byte_out	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
MIPI_CLK_RX_P	Setup	0.000	0
MIPI_CLK_RX_P	Hold	0.000	0
clkx2x4	Setup	0.000	0
clkx2x4	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.798	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.011	6.546
2	3.809	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.074	6.621
3	3.961	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.018	6.412
4	4.007	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.000	6.349
5	4.059	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_13_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.009	6.306
6	4.085	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_0_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.000	6.271
7	4.087	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.042	6.311
8	4.117	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.017	6.255
9	4.134	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.029	6.251
10	4.136	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_15_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.021	6.241
11	4.155	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_15_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.010	6.210
12	4.180	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_10_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.003	6.172
13	4.221	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_14_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.012	6.146
14	4.222	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.042	6.176
15	4.234	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.012	6.134
16	4.239	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_3_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.012	6.129
17	4.254	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.012	6.114
18	4.257	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.017	6.115
19	4.259	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.031	6.128
20	4.263	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_10_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.012	6.105
21	4.266	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_7_s0/D	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.006	6.331
22	4.323	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.000	6.032
23	4.328	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_14_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.042	6.070
24	4.329	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_12_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	-0.015	6.042
25	4.339	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CE	clk_byte_out:[R]	clk_byte_out:[R]	10.667	0.014	6.003

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.151	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/delay_update_n_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini1/VALUE	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.010	0.141
2	0.161	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/delay_update_n_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini0/VALUE	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.020	0.141
3	0.163	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/delay_update_n_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini2/VALUE	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.022	0.141
4	0.164	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_n_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini3/VALUE	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.023	0.141
5	0.212	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.026	0.223
6	0.236	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[9]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.020	0.253
7	0.245	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[13]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.002	0.284
8	0.245	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[12]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.002	0.284
9	0.252	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.026	0.263
10	0.274	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[11]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.014	0.295
11	0.275	gw_gao_inst_0/u_la0_top/bit_count_6_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_6_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
12	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
13	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
14	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
15	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
16	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.026	0.286
17	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[12]	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.026	0.286
18	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
19	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
20	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
21	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
22	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
23	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
24	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300
25	0.275	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1/D	clk_byte_out:[R]	clk_byte_out:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.279	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[F]	5.000	1.636	2.935
2	0.279	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[F]	5.000	1.636	2.935
3	0.298	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[F]	5.000	1.636	2.916
4	0.298	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[F]	5.000	1.636	2.916
5	2.595	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.080	2.311
6	2.595	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.080	2.311
7	2.597	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.077	2.313
8	2.597	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.077	2.313
9	2.597	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.077	2.313
10	2.597	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.077	2.313
11	2.602	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.073	2.311
12	2.604	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.071	2.311
13	2.604	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.071	2.311
14	5.268	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	10.000	1.645	2.935
15	5.268	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	10.000	1.645	2.935
16	5.287	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	10.000	1.645	2.916
17	5.287	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	10.000	1.645	2.916
18	2.729	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.045	2.213
19	2.729	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.045	2.213
20	2.729	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.045	2.213
21	2.729	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.045	2.213
22	2.732	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.042	2.213
23	2.798	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.078	2.110
24	2.804	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.063	2.119
25	2.804	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk_byte_out:[F]	clk_byte_out:[R]	5.334	0.063	2.119

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.554	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/PRESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.014	1.521
2	1.554	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLEAR	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.014	1.521
3	1.554	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLEAR	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.014	1.521
4	1.554	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLEAR	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.014	1.521
5	1.961	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.583	1.522
6	1.961	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.583	1.522
7	1.969	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.583	1.530
8	1.969	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/RESET	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.583	1.530
9	2.008	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/RESETN	clkx2x4:[R]	MIPI_CLK_RX_P:[R]	0.000	0.583	1.469
10	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_1_13_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
11	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_0_13_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
12	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_7_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
13	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
14	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_1_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
15	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg3_1_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
16	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
17	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
18	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_5_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.005	2.475
19	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_3_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479
20	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_1_14_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479
21	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_5_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479
22	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_14_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479
23	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_3_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479
24	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_6_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479
25	2.523	rx_hs_en_mask_s0/Q	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg2_3_s0/CLEAR	clk_byte_out:[R]	clk_byte_out:[R]	0.000	-0.009	2.479

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.241	4.241	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
2	3.241	4.241	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
3	3.246	4.246	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
4	3.246	4.246	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
5	3.246	4.246	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
6	3.246	4.246	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
7	3.252	4.252	1.000	Low Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
8	3.303	4.303	1.000	High Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
9	3.303	4.303	1.000	High Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
10	3.308	4.308	1.000	High Pulse Width	clk_byte_out	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.798
Data Arrival Time	8.324
Data Required Time	12.122
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.778	1.778	tNET	RR	1	R9C26[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.160	0.382	tC2Q	RR	20	R9C26[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.181	1.021	tNET	RR	1	R13C24[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n718_s10/I0
3.703	0.521	tINS	RR	13	R13C24[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n718_s10/F
4.635	0.933	tNET	RR	1	R17C26[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s5/I0
5.161	0.526	tINS	RR	1	R17C26[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s5/F
5.164	0.003	tNET	RR	1	R17C26[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s4/I1
5.690	0.526	tINS	RR	2	R17C26[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s4/F
5.924	0.234	tNET	RR	1	R13C25[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s2/I0
6.421	0.498	tINS	RR	16	R13C25[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s2/F
7.660	1.239	tNET	RR	1	R16C30[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n849_s0/I3
8.186	0.526	tINS	RR	1	R16C30[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n849_s0/F
8.324	0.137	tNET	RR	1	R16C30[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.433	1.766	tNET	RR	1	R16C30[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0/CLK
12.122	-0.311	tSu		1	R16C30[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_6_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.778, 100.000%
Arrival Data Path Delay	cell: 2.597, 39.679%; route: 3.566, 54.478%; tC2Q: 0.382, 5.843%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.766, 100.000%

Path2

Path Summary:

Slack	3.809
Data Arrival Time	8.358
Data Required Time	12.167
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
7.616	1.106	tNET	RR	1	R21C16[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n858_s0/I3
8.031	0.415	tINS	RR	1	R21C16[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n858_s0/F
8.358	0.327	tNET	RR	1	R21C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.478	1.811	tNET	RR	1	R21C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0/CLK
12.167	-0.311	tSu		1	R21C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_15_s0

Path Statistics:

Clock Skew	0.074
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 1.991, 30.074%; route: 4.247, 64.150%; tC2Q: 0.382, 5.777%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.811, 100.000%

Path3

Path Summary:

Slack	3.961
Data Arrival Time	8.159
Data Required Time	12.120
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.495	0.856	tNET	RR	1	R33C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n850_s0/I3
8.022	0.526	tINS	RR	1	R33C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n850_s0/F
8.159	0.137	tNET	RR	1	R33C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.431	1.764	tNET	RR	1	R33C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0/CLK
12.120	-0.311	tSu		1	R33C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_7_s0

Path Statistics:

Clock Skew	0.018
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.445, 38.129%; route: 3.600, 56.140%; tC2Q: 0.368, 5.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.764, 100.000%

Path4

Path Summary:

Slack	4.007
Data Arrival Time	8.107
Data Required Time	12.114
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.758	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
2.126	0.368	tC2Q	RF	24	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q
2.705	0.579	tNET	FF	1	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/I0
3.231	0.526	tINS	FR	10	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/F
4.332	1.101	tNET	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/I3
4.853	0.521	tINS	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/F
5.011	0.157	tNET	RR	1	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/I3
5.508	0.498	tINS	RR	2	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/F
6.008	0.500	tNET	RR	1	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/I0
6.271	0.262	tINS	RR	16	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/F
7.243	0.972	tNET	RR	1	R33C15[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n849_s0/I3
7.760	0.516	tINS	RR	1	R33C15[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n849_s0/F
8.107	0.347	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.425	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
12.114	-0.311	tSu		1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%
Arrival Data Path Delay	cell: 2.324, 36.602%; route: 3.658, 57.610%; tC2Q: 0.368, 5.789%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%

Path5

Path Summary:

Slack	4.059
Data Arrival Time	8.065
Data Required Time	12.124
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.758	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
2.126	0.368	tC2Q	RF	24	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q
2.705	0.579	tNET	FF	1	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/I0
3.231	0.526	tINS	FR	10	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/F
4.332	1.101	tNET	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/I3
4.853	0.521	tINS	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/F
5.011	0.157	tNET	RR	1	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/I3
5.508	0.498	tINS	RR	2	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/F
6.008	0.500	tNET	RR	1	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/I0
6.271	0.262	tINS	RR	16	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/F
7.191	0.920	tNET	RR	1	R35C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n856_s0/I3
7.717	0.526	tINS	RR	1	R35C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n856_s0/F
8.065	0.347	tNET	RR	1	R32C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.435	1.768	tNET	RR	1	R32C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_13_s0/CLK
12.124	-0.311	tSu		1	R32C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_13_s0

Path Statistics:

Clock Skew	0.009
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%
Arrival Data Path Delay	cell: 2.334, 37.007%; route: 3.605, 57.166%; tC2Q: 0.368, 5.828%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.768, 100.000%

Path6

Path Summary:

Slack	4.085
Data Arrival Time	8.030
Data Required Time	12.114
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_0_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.758	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
2.126	0.368	tC2Q	RF	24	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q
2.705	0.579	tNET	FF	1	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/I0
3.231	0.526	tINS	FR	10	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/F
4.332	1.101	tNET	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/I3
4.853	0.521	tINS	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/F
5.011	0.157	tNET	RR	1	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/I3
5.508	0.498	tINS	RR	2	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/F
6.008	0.500	tNET	RR	1	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/I0
6.271	0.262	tINS	RR	16	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/F
6.803	0.532	tNET	RR	1	R32C18[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n843_s0/I3
7.265	0.461	tINS	RR	1	R32C18[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n843_s0/F
8.030	0.765	tNET	RR	1	R32C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.425	1.758	tNET	RR	1	R32C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_0_s0/CLK
12.114	-0.311	tSu		1	R32C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%
Arrival Data Path Delay	cell: 2.269, 36.177%; route: 3.635, 57.963%; tC2Q: 0.368, 5.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%

Path7

Path Summary:

Slack	4.087
Data Arrival Time	8.048
Data Required Time	12.135
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
7.450	0.940	tNET	RR	1	R18C17[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n856_s0/I3
7.911	0.461	tINS	RR	1	R18C17[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n856_s0/F
8.048	0.137	tNET	RR	1	R18C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.446	1.779	tNET	RR	1	R18C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0/CLK
12.135	-0.311	tSu		1	R18C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_13_s0

Path Statistics:

Clock Skew	0.042
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 2.037, 32.284%; route: 3.891, 61.656%; tC2Q: 0.382, 6.061%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.779, 100.000%

Path8

Path Summary:

Slack	4.117
Data Arrival Time	8.002
Data Required Time	12.119
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.338	0.699	tNET	RR	1	R29C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n849_s0/I3
7.864	0.526	tINS	RR	1	R29C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n849_s0/F
8.002	0.137	tNET	RR	1	R29C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.430	1.763	tNET	RR	1	R29C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CLK
12.119	-0.311	tSu		1	R29C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.445, 39.089%; route: 3.443, 55.036%; tC2Q: 0.368, 5.875%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.763, 100.000%

Path9

Path Summary:

Slack	4.134
Data Arrival Time	7.998
Data Required Time	12.131
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.334	0.695	tNET	RR	1	R34C21[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s0/I3
7.860	0.526	tINS	RR	1	R34C21[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n856_s0/F
7.998	0.137	tNET	RR	1	R34C21[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.443	1.776	tNET	RR	1	R34C21[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0/CLK
12.131	-0.311	tSu		1	R34C21[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_13_s0

Path Statistics:

Clock Skew	0.029
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.445, 39.112%; route: 3.439, 55.009%; tC2Q: 0.368, 5.879%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.776, 100.000%

Path10

Path Summary:

Slack	4.136
Data Arrival Time	7.988
Data Required Time	12.124
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_15_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.199	0.560	tNET	RR	1	R34C21[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n858_s0/I3
7.660	0.461	tINS	RR	1	R34C21[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n858_s0/F
7.988	0.327	tNET	RR	1	R32C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.435	1.768	tNET	RR	1	R32C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_15_s0/CLK
12.124	-0.311	tSu		1	R32C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_15_s0

Path Statistics:

Clock Skew	0.021
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.380, 38.133%; route: 3.494, 55.978%; tC2Q: 0.368, 5.888%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.768, 100.000%

Path11

Path Summary:

Slack	4.155
Data Arrival Time	7.968
Data Required Time	12.124
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_15_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.758	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
2.126	0.368	tC2Q	RF	24	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q
2.705	0.579	tNET	FF	1	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/I0
3.231	0.526	tINS	FR	10	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/F
4.332	1.101	tNET	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/I3
4.853	0.521	tINS	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/F
5.011	0.157	tNET	RR	1	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/I3
5.508	0.498	tINS	RR	2	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/F
6.008	0.500	tNET	RR	1	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/I0
6.271	0.262	tINS	RR	16	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/F
7.568	1.298	tNET	RR	1	R35C14[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n858_s0/I3
7.831	0.262	tINS	RR	1	R35C14[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n858_s0/F
7.968	0.137	tNET	RR	1	R35C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_15_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.435	1.768	tNET	RR	1	R35C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_15_s0/CLK
12.124	-0.311	tSu		1	R35C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_15_s0

Path Statistics:

Clock Skew	0.010
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%
Arrival Data Path Delay	cell: 2.070, 33.333%; route: 3.773, 60.749%; tC2Q: 0.368, 5.918%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.768, 100.000%

Path12

Path Summary:

Slack	4.180
Data Arrival Time	7.931
Data Required Time	12.111
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_10_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.758	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
2.126	0.368	tC2Q	RF	24	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q
2.705	0.579	tNET	FF	1	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/I0
3.231	0.526	tINS	FR	10	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/F
4.332	1.101	tNET	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/I3
4.853	0.521	tINS	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/F
5.011	0.157	tNET	RR	1	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/I3
5.508	0.498	tINS	RR	2	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/F
6.008	0.500	tNET	RR	1	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/I0
6.271	0.262	tINS	RR	16	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/F
7.378	1.107	tNET	RR	1	R33C15[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n853_s0/I3
7.793	0.415	tINS	RR	1	R33C15[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n853_s0/F
7.931	0.137	tNET	RR	1	R33C15[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.422	1.755	tNET	RR	1	R33C15[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_10_s0/CLK
12.111	-0.311	tSu		1	R33C15[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_10_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%
Arrival Data Path Delay	cell: 2.223, 36.006%; route: 3.583, 58.040%; tC2Q: 0.368, 5.954%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.755, 100.000%

Path13

Path Summary:

Slack	4.221
Data Arrival Time	7.893
Data Required Time	12.114
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_14_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.234	0.595	tNET	RR	1	R32C20[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n857_s0/I3
7.755	0.521	tINS	RR	1	R32C20[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n857_s0/F
7.893	0.137	tNET	RR	1	R32C20[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.425	1.758	tNET	RR	1	R32C20[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_14_s0/CLK
12.114	-0.311	tSu		1	R32C20[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_14_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.440, 39.699%; route: 3.339, 54.322%; tC2Q: 0.368, 5.979%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%

Path14

Path Summary:

Slack	4.222
Data Arrival Time	7.913
Data Required Time	12.135
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
7.260	0.750	tNET	RR	1	R18C17[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n855_s0/I3
7.776	0.516	tINS	RR	1	R18C17[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n855_s0/F
7.913	0.137	tNET	RR	1	R18C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.446	1.779	tNET	RR	1	R18C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0/CLK
12.135	-0.311	tSu		1	R18C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0

Path Statistics:

Clock Skew	0.042
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 2.092, 33.880%; route: 3.701, 59.927%; tC2Q: 0.382, 6.193%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.779, 100.000%

Path15

Path Summary:

Slack	4.234
Data Arrival Time	7.871
Data Required Time	12.105
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
7.207	0.697	tNET	RR	1	R14C19[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n845_s0/I3
7.733	0.526	tINS	RR	1	R14C19[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n845_s0/F
7.871	0.137	tNET	RR	1	R14C19[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.416	1.749	tNET	RR	1	R14C19[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0/CLK
12.105	-0.311	tSu		1	R14C19[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_2_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 2.102, 34.278%; route: 3.649, 59.486%; tC2Q: 0.382, 6.236%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.749, 100.000%

Path16

Path Summary:

Slack	4.239
Data Arrival Time	7.866
Data Required Time	12.105
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
7.207	0.697	tNET	RR	1	R14C19[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n846_s0/I3
7.728	0.521	tINS	RR	1	R14C19[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n846_s0/F
7.866	0.137	tNET	RR	1	R14C19[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.416	1.749	tNET	RR	1	R14C19[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_3_s0/CLK
12.105	-0.311	tSu		1	R14C19[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_3_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 2.097, 34.224%; route: 3.649, 59.535%; tC2Q: 0.382, 6.241%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.749, 100.000%

Path17

Path Summary:

Slack	4.254
Data Arrival Time	7.860
Data Required Time	12.114
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.007	0.368	tNET	RR	1	R32C21[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s0/I3
7.533	0.526	tINS	RR	1	R32C21[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s0/F
7.860	0.327	tNET	RR	1	R32C22[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.425	1.758	tNET	RR	1	R32C22[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0/CLK
12.114	-0.311	tSu		1	R32C22[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_1_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.445, 39.992%; route: 3.301, 53.997%; tC2Q: 0.368, 6.011%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%

Path18

Path Summary:

Slack	4.257
Data Arrival Time	7.862
Data Required Time	12.119
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.203	0.564	tNET	RR	1	R29C28[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n848_s0/I3
7.724	0.521	tINS	RR	1	R29C28[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n848_s0/F
7.862	0.137	tNET	RR	1	R29C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.430	1.763	tNET	RR	1	R29C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLK
12.119	-0.311	tSu		1	R29C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0

Path Statistics:

Clock Skew	0.017
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.440, 39.902%; route: 3.308, 54.088%; tC2Q: 0.368, 6.010%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.763, 100.000%

Path19

Path Summary:

Slack	4.259
Data Arrival Time	7.865
Data Required Time	12.124
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
6.875	0.365	tNET	RR	1	R14C17[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n854_s0/I3
7.137	0.262	tINS	RR	1	R14C17[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n854_s0/F
7.865	0.728	tNET	RR	1	R14C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.435	1.768	tNET	RR	1	R14C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0/CLK
12.124	-0.311	tSu		1	R14C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_11_s0

Path Statistics:

Clock Skew	0.031
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 1.839, 30.008%; route: 3.906, 63.749%; tC2Q: 0.382, 6.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.768, 100.000%

Path20

Path Summary:

Slack	4.263
Data Arrival Time	7.852
Data Required Time	12.114
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_10_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.007	0.368	tNET	RR	1	R32C21[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n853_s0/I3
7.504	0.498	tINS	RR	1	R32C21[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n853_s0/F
7.852	0.347	tNET	RR	1	R32C22[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.425	1.758	tNET	RR	1	R32C22[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_10_s0/CLK
12.114	-0.311	tSu		1	R32C22[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_10_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.416, 39.578%; route: 3.321, 54.402%; tC2Q: 0.368, 6.020%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%

Path21

Path Summary:

Slack	4.266
Data Arrival Time	8.111
Data Required Time	12.377
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_7_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.779	1.779	tNET	RR	1	R18C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0/CLK
2.162	0.382	tC2Q	RR	21	R18C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_12_s0/Q
3.232	1.070	tNET	RR	1	R13C15[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s5/I1
3.758	0.526	tINS	RR	11	R13C15[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s5/F
6.096	2.337	tNET	RR	1	R17C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s10/I0
6.358	0.262	tINS	RR	1	R17C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s10/F
6.516	0.157	tNET	RR	1	R16C22[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s4/I1
6.778	0.262	tINS	RR	1	R16C22[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s4/F
6.781	0.003	tNET	RR	1	R16C22[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s1/I0
7.302	0.521	tINS	RR	1	R16C22[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s1/F
7.649	0.347	tNET	RR	1	R15C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s0/I1
8.111	0.461	tINS	RR	1	R15C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n722_s0/F
8.111	0.000	tNET	RR	1	R15C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.441	1.774	tNET	RR	1	R15C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_7_s0/CLK
12.377	-0.064	tSu		1	R15C21[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/dout_7_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.779, 100.000%
Arrival Data Path Delay	cell: 2.034, 32.122%; route: 3.915, 61.836%; tC2Q: 0.382, 6.041%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.774, 100.000%

Path22

Path Summary:

Slack	4.323
Data Arrival Time	7.779
Data Required Time	12.102
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.747	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
2.114	0.368	tC2Q	RF	21	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/Q
3.780	1.666	tNET	FF	1	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/I1
4.297	0.516	tINS	FR	10	R34C22[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n714_s9/F
4.884	0.587	tNET	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/I2
5.345	0.461	tINS	RR	1	R30C23[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s8/F
5.348	0.003	tNET	RR	1	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/I2
5.763	0.415	tINS	RR	2	R30C23[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s4/F
6.113	0.350	tNET	RR	1	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/I0
6.639	0.526	tINS	RR	16	R31C22[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n844_s2/F
7.115	0.476	tNET	RR	1	R30C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n847_s0/I3
7.642	0.526	tINS	RR	1	R30C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/n847_s0/F
7.779	0.137	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.414	1.747	tNET	RR	1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0/CLK
12.102	-0.311	tSu		1	R30C28[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%
Arrival Data Path Delay	cell: 2.445, 40.530%; route: 3.220, 53.378%; tC2Q: 0.368, 6.092%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.747, 100.000%

Path23

Path Summary:

Slack	4.328
Data Arrival Time	7.807
Data Required Time	12.135
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_14_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.737	1.737	tNET	RR	1	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/CLK
2.120	0.382	tC2Q	RR	19	R12C15[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_9_s0/Q
3.388	1.269	tNET	RR	1	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/I0
3.886	0.498	tINS	RR	13	R20C16[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n715_s11/F
5.097	1.211	tNET	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/I2
5.360	0.262	tINS	RR	1	R14C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s6/F
5.362	0.003	tNET	RR	1	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/I3
5.652	0.290	tINS	RF	2	R14C18[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/sync_found_s4/F
5.983	0.331	tNET	FF	1	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/I0
6.510	0.526	tINS	FR	16	R13C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n844_s2/F
7.255	0.745	tNET	RR	1	R18C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n857_s0/I3
7.670	0.415	tINS	RR	1	R18C17[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/n857_s0/F
7.807	0.137	tNET	RR	1	R18C17[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.446	1.779	tNET	RR	1	R18C17[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_14_s0/CLK
12.135	-0.311	tSu		1	R18C17[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd1/shftamt_14_s0

Path Statistics:

Clock Skew	0.042
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.737, 100.000%
Arrival Data Path Delay	cell: 1.991, 32.805%; route: 3.696, 60.894%; tC2Q: 0.382, 6.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.779, 100.000%

Path24

Path Summary:

Slack	4.329
Data Arrival Time	7.801
Data Required Time	12.130
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_12_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.758	1.758	tNET	RR	1	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/CLK
2.126	0.368	tC2Q	RF	24	R32C14[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_6_s0/Q
2.705	0.579	tNET	FF	1	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/I0
3.231	0.526	tINS	FR	10	R30C16[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n715_s1/F
4.332	1.101	tNET	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/I3
4.853	0.521	tINS	RR	1	R24C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s6/F
5.011	0.157	tNET	RR	1	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/I3
5.508	0.498	tINS	RR	2	R24C18[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/sync_found_s4/F
6.008	0.500	tNET	RR	1	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/I0
6.271	0.262	tINS	RR	16	R30C16[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n844_s2/F
6.998	0.727	tNET	RR	1	R34C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n855_s0/I3
7.263	0.265	tINS	RR	1	R34C17[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n855_s0/F
7.801	0.537	tNET	RR	1	R33C17[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_12_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.441	1.774	tNET	RR	1	R33C17[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_12_s0/CLK
12.130	-0.311	tSu		1	R33C17[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/shftamt_12_s0

Path Statistics:

Clock Skew	0.015
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.758, 100.000%
Arrival Data Path Delay	cell: 2.073, 34.299%; route: 3.602, 59.619%; tC2Q: 0.368, 6.082%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.774, 100.000%

Path25

Path Summary:

Slack	4.339
Data Arrival Time	7.780
Data Required Time	12.119
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.778	1.778	tNET	RR	1	R9C26[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/CLK
2.160	0.382	tC2Q	RR	20	R9C26[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_11_s0/Q
3.181	1.021	tNET	RR	1	R13C24[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n718_s10/I0
3.703	0.521	tINS	RR	13	R13C24[3][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n718_s10/F
4.635	0.933	tNET	RR	1	R17C26[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s5/I0
5.161	0.526	tINS	RR	1	R17C26[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s5/F
5.164	0.003	tNET	RR	1	R17C26[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s4/I1
5.690	0.526	tINS	RR	2	R17C26[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/sync_found_s4/F
5.924	0.234	tNET	RR	1	R13C25[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s2/I0
6.421	0.498	tINS	RR	16	R13C25[3][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n844_s2/F
7.116	0.695	tNET	RR	1	R11C24[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n846_s0/I3
7.642	0.526	tINS	RR	1	R11C24[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/n846_s0/F
7.780	0.137	tNET	RR	1	R11C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.430	1.763	tNET	RR	1	R11C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CLK
12.119	-0.311	tSu		1	R11C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0

Path Statistics:

Clock Skew	-0.014
Setup Relationship	10.667
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.778, 100.000%
Arrival Data Path Delay	cell: 2.597, 43.274%; route: 3.023, 50.354%; tC2Q: 0.382, 6.372%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.763, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.151
Data Arrival Time	0.871
Data Required Time	0.720
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/delay_update_n_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.730	0.730	tNET	RR	1	R9C16[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/delay_update_n_s0/CLK
0.871	0.141	tC2Q	RF	1	R9C16[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/delay_update_n_s0/Q
0.871	0.000	tNET	FF	1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini1/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/PCLK
0.720	0.000	tHld		1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini1

Path Statistics:

Clock Skew	-0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.730, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.141, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path2

Path Summary:

Slack	0.161
Data Arrival Time	0.881
Data Required Time	0.720
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/delay_update_n_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.740	0.740	tNET	RR	1	R7C14[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/delay_update_n_s0/CLK
0.881	0.141	tC2Q	RF	1	R7C14[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/delay_update_n_s0/Q
0.881	0.000	tNET	FF	1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini0/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/PCLK
0.720	0.000	tHld		1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini0

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.740, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.141, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path3

Path Summary:

Slack	0.163
Data Arrival Time	0.883
Data Required Time	0.720
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/delay_update_n_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini2
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.742	0.742	tNET	RR	1	R6C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/delay_update_n_s0/CLK
0.883	0.141	tC2Q	RF	1	R6C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/delay_update_n_s0/Q
0.883	0.000	tNET	FF	1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini2/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/PCLK
0.720	0.000	tHld		1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini2

Path Statistics:

Clock Skew	-0.022
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.742, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.141, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path4

Path Summary:

Slack	0.164
Data Arrival Time	0.884
Data Required Time	0.720
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_n_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini3
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.743	0.743	tNET	RR	1	R21C23[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_n_s0/CLK
0.884	0.141	tC2Q	RF	1	R21C23[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_n_s0/Q
0.884	0.000	tNET	FF	1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini3/VALUE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/PCLK
0.720	0.000	tHld		1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/udel_dataini3

Path Statistics:

Clock Skew	-0.023
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.743, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.141, 100.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path5

Path Summary:

Slack	0.212
Data Arrival Time	0.970
Data Required Time	0.758
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.747	0.747	tNET	RR	1	R21C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
0.888	0.141	tC2Q	RF	1	R21C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
0.970	0.082	tNET	FF	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.721	0.721	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.758	0.037	tHld		1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.747, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.082, 36.771%; tC2Q: 0.141, 63.229%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.721, 100.000%

Path6

Path Summary:

Slack	0.236
Data Arrival Time	0.994
Data Required Time	0.758
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.741	0.741	tNET	RR	1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.882	0.141	tC2Q	RF	11	R22C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
0.994	0.112	tNET	FF	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.721	0.721	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.758	0.037	tHld		1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.741, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.112, 44.269%; tC2Q: 0.141, 55.731%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.721, 100.000%

Path7

Path Summary:

Slack	0.245
Data Arrival Time	1.011
Data Required Time	0.766
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.727	0.727	tNET	RR	1	R18C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/CLK
0.871	0.144	tC2Q	RR	1	R18C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/Q
1.011	0.140	tNET	RR	1	BSRAM_R28[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.729	0.729	tNET	RR	1	BSRAM_R28[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
0.766	0.037	tHld		1	BSRAM_R28[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.727, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.729, 100.000%

Path8

Path Summary:

Slack	0.245
Data Arrival Time	1.011
Data Required Time	0.766
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.727	0.727	tNET	RR	1	R18C42[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0/CLK
0.871	0.144	tC2Q	RR	1	R18C42[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0/Q
1.011	0.140	tNET	RR	1	BSRAM_R28[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.729	0.729	tNET	RR	1	BSRAM_R28[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
0.766	0.037	tHld		1	BSRAM_R28[8][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.727, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.729, 100.000%

Path9

Path Summary:

Slack	0.252
Data Arrival Time	1.010
Data Required Time	0.758
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.747	0.747	tNET	RR	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
0.888	0.141	tC2Q	RF	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
1.010	0.122	tNET	FF	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.721	0.721	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.758	0.037	tHld		1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.747, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 46.388%; tC2Q: 0.141, 53.612%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.721, 100.000%

Path10

Path Summary:

Slack	0.274
Data Arrival Time	3.030
Data Required Time	2.756
From	gw_gao_inst_0/u_la0_top/address_counter_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R41C48	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	407	R41C48	gw_gao_inst_0/u_gw_jtag/tck_o
2.735	1.385	tNET	RR	1	R23C37[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.879	0.144	tC2Q	RR	10	R23C37[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q
3.030	0.151	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADB[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R41C48	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	407	R41C48	gw_gao_inst_0/u_gw_jtag/tck_o
2.721	1.370	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB
2.756	0.035	tHld		1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 49.388%; route: 1.385, 50.612%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.151, 51.186%; tC2Q: 0.144, 48.814%
Required Clock Path Delay	cell: 1.351, 49.651%; route: 1.370, 50.349%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	3.030
Data Required Time	2.755
From	gw_gao_inst_0/u_la0_top/bit_count_6_s1
To	gw_gao_inst_0/u_la0_top/bit_count_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R41C48	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	407	R41C48	gw_gao_inst_0/u_gw_jtag/tck_o
2.730	1.379	tNET	RR	1	R6C34[1][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/CLK
2.871	0.141	tC2Q	RF	3	R6C34[1][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/Q
2.877	0.006	tNET	FF	1	R6C34[1][A]	gw_gao_inst_0/u_la0_top/n875_s2/I1
3.030	0.153	tINS	FF	1	R6C34[1][A]	gw_gao_inst_0/u_la0_top/n875_s2/F
3.030	0.000	tNET	FF	1	R6C34[1][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOL20[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R41C48	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	407	R41C48	gw_gao_inst_0/u_gw_jtag/tck_o
2.730	1.379	tNET	RR	1	R6C34[1][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1/CLK
2.755	0.025	tHld		1	R6C34[1][A]	gw_gao_inst_0/u_la0_top/bit_count_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 49.492%; route: 1.379, 50.508%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 49.492%; route: 1.379, 50.508%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.049
Data Required Time	0.774
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.749	0.749	tNET	RR	1	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
0.890	0.141	tC2Q	RF	10	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
0.896	0.006	tNET	FF	1	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n761_s1/I2
1.049	0.153	tINS	FF	1	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n761_s1/F
1.049	0.000	tNET	FF	1	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.749	0.749	tNET	RR	1	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
0.774	0.025	tHld		1	R22C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.749, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.749, 100.000%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.034
Data Required Time	0.759
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.734	0.734	tNET	RR	1	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0/CLK
0.875	0.141	tC2Q	RF	4	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0/Q
0.881	0.006	tNET	FF	1	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n249_s0/I2
1.034	0.153	tINS	FF	1	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n249_s0/F
1.034	0.000	tNET	FF	1	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.734	0.734	tNET	RR	1	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0/CLK
0.759	0.025	tHld		1	R27C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.734, 100.000%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.044
Data Required Time	0.769
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.744	0.744	tNET	RR	1	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9/CLK
0.885	0.141	tC2Q	RF	3	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9/Q
0.891	0.006	tNET	FF	1	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/n174_s11/I1
1.044	0.153	tINS	FF	1	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/n174_s11/F
1.044	0.000	tNET	FF	1	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.744	0.744	tNET	RR	1	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9/CLK
0.769	0.025	tHld		1	R7C21[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/sync_found_s9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.744, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.744, 100.000%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.034
Data Required Time	0.759
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.734	0.734	tNET	RR	1	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1/CLK
0.875	0.141	tC2Q	RF	4	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1/Q
0.881	0.006	tNET	FF	1	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/n210_s2/I2
1.034	0.153	tINS	FF	1	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/n210_s2/F
1.034	0.000	tNET	FF	1	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.734	0.734	tNET	RR	1	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1/CLK
0.759	0.025	tHld		1	R9C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane1/hs_sync_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.734, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.734, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.033
Data Required Time	0.758
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.747	0.747	tNET	RR	1	R21C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
0.888	0.141	tC2Q	RF	1	R21C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.033	0.145	tNET	FF	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.721	0.721	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.758	0.037	tHld		1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.747, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.145, 50.699%; tC2Q: 0.141, 49.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.721, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.033
Data Required Time	0.758
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.747	0.747	tNET	RR	1	R21C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK
0.888	0.141	tC2Q	RF	1	R21C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q
1.033	0.145	tNET	FF	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.721	0.721	tNET	RR	1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.758	0.037	tHld		1	BSRAM_R28[6][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.026
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.747, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.145, 50.699%; tC2Q: 0.141, 49.301%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.721, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	1.045
Data Required Time	0.770
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.745	0.745	tNET	RR	1	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2/CLK
0.886	0.141	tC2Q	RF	2	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2/Q
0.892	0.006	tNET	FF	1	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/n159_s12/I2
1.045	0.153	tINS	FF	1	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/n159_s12/F
1.045	0.000	tNET	FF	1	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.745	0.745	tNET	RR	1	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2/CLK
0.770	0.025	tHld		1	R20C23[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/delay_update_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.745, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.745, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.043
Data Required Time	0.768
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.743	0.743	tNET	RR	1	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1/CLK
0.884	0.141	tC2Q	RF	3	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1/Q
0.890	0.006	tNET	FF	1	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/n206_s2/I3
1.043	0.153	tINS	FF	1	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/n206_s2/F
1.043	0.000	tNET	FF	1	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.743	0.743	tNET	RR	1	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1/CLK
0.768	0.025	tHld		1	R21C27[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/hs_sync_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.743, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.743, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.043
Data Required Time	0.768
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.743	0.743	tNET	RR	1	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0/CLK
0.884	0.141	tC2Q	RF	2	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0/Q
0.890	0.006	tNET	FF	1	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/n275_s2/I0
1.043	0.153	tINS	FF	1	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/n275_s2/F
1.043	0.000	tNET	FF	1	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.743	0.743	tNET	RR	1	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0/CLK
0.768	0.025	tHld		1	R21C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane3/window_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.743, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.743, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.042
Data Required Time	0.767
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.742	0.742	tNET	RR	1	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3/CLK
0.883	0.141	tC2Q	RF	5	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3/Q
0.889	0.006	tNET	FF	1	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/n174_s12/I1
1.042	0.153	tINS	FF	1	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/n174_s12/F
1.042	0.000	tNET	FF	1	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.742	0.742	tNET	RR	1	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3/CLK
0.767	0.025	tHld		1	R6C18[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_active_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.742, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.742, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.042
Data Required Time	0.767
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.742	0.742	tNET	RR	1	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3/CLK
0.883	0.141	tC2Q	RF	5	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3/Q
0.889	0.006	tNET	FF	1	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/n174_s12/I1
1.042	0.153	tINS	FF	1	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/n174_s12/F
1.042	0.000	tNET	FF	1	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.742	0.742	tNET	RR	1	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3/CLK
0.767	0.025	tHld		1	R6C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane0/hs_active_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.742, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.742, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.039
Data Required Time	0.764
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.739	0.739	tNET	RR	1	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLK
0.880	0.141	tC2Q	RF	5	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/Q
0.886	0.006	tNET	FF	1	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n364_s4/I3
1.039	0.153	tINS	FF	1	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n364_s4/F
1.039	0.000	tNET	FF	1	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.739	0.739	tNET	RR	1	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1/CLK
0.764	0.025	tHld		1	R26C25[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane3_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.739, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.739, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.026
Data Required Time	0.751
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.726	0.726	tNET	RR	1	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLK
0.867	0.141	tC2Q	RF	5	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/Q
0.873	0.006	tNET	FF	1	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n250_s4/I3
1.026	0.153	tINS	FF	1	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/n250_s4/F
1.026	0.000	tNET	FF	1	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.726	0.726	tNET	RR	1	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1/CLK
0.751	0.025	tHld		1	R27C27[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/lane2_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.036
Data Required Time	0.761
From	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.736	0.736	tNET	RR	1	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1/CLK
0.877	0.141	tC2Q	RF	4	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1/Q
0.883	0.006	tNET	FF	1	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/n210_s2/I2
1.036	0.153	tINS	FF	1	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/n210_s2/F
1.036	0.000	tNET	FF	1	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.736	0.736	tNET	RR	1	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1/CLK
0.761	0.025	tHld		1	R7C19[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/iodelay_scan_lane2/hs_sync_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.736, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.736, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.279
Data Arrival Time	5.444
Data Required Time	5.724
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.444	2.568	tNET	FF	16	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					MIPI_CLK_RX_P
5.000	0.000	tCL	FF	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
5.688	0.688	tINS	FF	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.688	0.000	tNET	FF	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.873	0.186	tINS	FF	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.873	0.000	tNET	FF	1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/FCLK
5.839	-0.035	tUnc
5.724	-0.115	tSu		1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1

Path Statistics:

Clock Skew	-1.636
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.568, 87.479%; tC2Q: 0.368, 12.521%
Required Clock Path Delay	cell: 0.873, 100.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	0.279
Data Arrival Time	5.444
Data Required Time	5.724
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.444	2.568	tNET	FF	16	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					MIPI_CLK_RX_P
5.000	0.000	tCL	FF	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
5.688	0.688	tINS	FF	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.688	0.000	tNET	FF	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.873	0.186	tINS	FF	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.873	0.000	tNET	FF	1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/FCLK
5.839	-0.035	tUnc
5.724	-0.115	tSu		1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3

Path Statistics:

Clock Skew	-1.636
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.568, 87.479%; tC2Q: 0.368, 12.521%
Required Clock Path Delay	cell: 0.873, 100.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	0.298
Data Arrival Time	5.426
Data Required Time	5.724
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.426	2.549	tNET	FF	16	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					MIPI_CLK_RX_P
5.000	0.000	tCL	FF	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
5.688	0.688	tINS	FF	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.688	0.000	tNET	FF	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.873	0.186	tINS	FF	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.873	0.000	tNET	FF	1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/FCLK
5.839	-0.035	tUnc
5.724	-0.115	tSu		1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0

Path Statistics:

Clock Skew	-1.636
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.549, 87.398%; tC2Q: 0.368, 12.602%
Required Clock Path Delay	cell: 0.873, 100.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	0.298
Data Arrival Time	5.426
Data Required Time	5.724
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.426	2.549	tNET	FF	16	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					MIPI_CLK_RX_P
5.000	0.000	tCL	FF	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
5.688	0.688	tINS	FF	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
5.688	0.000	tNET	FF	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
5.873	0.186	tINS	FF	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
5.873	0.000	tNET	FF	1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/FCLK
5.839	-0.035	tUnc
5.724	-0.115	tSu		1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2

Path Statistics:

Clock Skew	-1.636
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.549, 87.398%; tC2Q: 0.368, 12.602%
Required Clock Path Delay	cell: 0.873, 100.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	2.595
Data Arrival Time	9.481
Data Required Time	12.076
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.481	1.869	tNET	FF	1	R16C43[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.424	1.757	tNET	RR	1	R16C43[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
12.076	-0.347	tSu		1	R16C43[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.080
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.869, 80.855%; tC2Q: 0.442, 19.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.757, 100.000%

Path6

Path Summary:

Slack	2.595
Data Arrival Time	9.481
Data Required Time	12.076
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.481	1.869	tNET	FF	1	R16C43[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.424	1.757	tNET	RR	1	R16C43[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
12.076	-0.347	tSu		1	R16C43[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.080
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.869, 80.855%; tC2Q: 0.442, 19.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.757, 100.000%

Path7

Path Summary:

Slack	2.597
Data Arrival Time	9.483
Data Required Time	12.080
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.483	1.870	tNET	FF	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.428	1.761	tNET	RR	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
12.080	-0.347	tSu		1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.077
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.870, 80.865%; tC2Q: 0.442, 19.135%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.761, 100.000%

Path8

Path Summary:

Slack	2.597
Data Arrival Time	9.483
Data Required Time	12.080
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.483	1.870	tNET	FF	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.428	1.761	tNET	RR	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
12.080	-0.347	tSu		1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.077
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.870, 80.865%; tC2Q: 0.442, 19.135%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.761, 100.000%

Path9

Path Summary:

Slack	2.597
Data Arrival Time	9.483
Data Required Time	12.080
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.483	1.870	tNET	FF	1	R18C43[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.428	1.761	tNET	RR	1	R18C43[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
12.080	-0.347	tSu		1	R18C43[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.077
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.870, 80.865%; tC2Q: 0.442, 19.135%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.761, 100.000%

Path10

Path Summary:

Slack	2.597
Data Arrival Time	9.483
Data Required Time	12.080
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.483	1.870	tNET	FF	1	R18C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.428	1.761	tNET	RR	1	R18C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
12.080	-0.347	tSu		1	R18C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.077
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.870, 80.865%; tC2Q: 0.442, 19.135%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.761, 100.000%

Path11

Path Summary:

Slack	2.602
Data Arrival Time	9.481
Data Required Time	12.084
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.481	1.869	tNET	FF	1	R15C42[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.431	1.764	tNET	RR	1	R15C42[0][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
12.084	-0.347	tSu		1	R15C42[0][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.073
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.869, 80.855%; tC2Q: 0.442, 19.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.764, 100.000%

Path12

Path Summary:

Slack	2.604
Data Arrival Time	9.481
Data Required Time	12.086
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.481	1.869	tNET	FF	1	R16C42[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.433	1.766	tNET	RR	1	R16C42[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
12.086	-0.347	tSu		1	R16C42[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.071
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.869, 80.855%; tC2Q: 0.442, 19.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.766, 100.000%

Path13

Path Summary:

Slack	2.604
Data Arrival Time	9.481
Data Required Time	12.086
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.481	1.869	tNET	FF	1	R16C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.433	1.766	tNET	RR	1	R16C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
12.086	-0.347	tSu		1	R16C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.071
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.869, 80.855%; tC2Q: 0.442, 19.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.766, 100.000%

Path14

Path Summary:

Slack	5.268
Data Arrival Time	5.444
Data Required Time	10.713
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.444	2.568	tNET	FF	16	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					MIPI_CLK_RX_P
10.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
10.682	0.683	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
10.682	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.865	0.182	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.865	0.000	tNET	RR	1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/FCLK
10.830	-0.035	tUnc
10.713	-0.117	tSu		1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3

Path Statistics:

Clock Skew	-1.645
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.568, 87.479%; tC2Q: 0.368, 12.521%
Required Clock Path Delay	cell: 0.864, 100.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	5.268
Data Arrival Time	5.444
Data Required Time	10.713
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.444	2.568	tNET	FF	16	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					MIPI_CLK_RX_P
10.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
10.682	0.683	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
10.682	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.865	0.182	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.865	0.000	tNET	RR	1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/FCLK
10.830	-0.035	tUnc
10.713	-0.117	tSu		1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1

Path Statistics:

Clock Skew	-1.645
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.568, 87.479%; tC2Q: 0.368, 12.521%
Required Clock Path Delay	cell: 0.864, 100.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	5.287
Data Arrival Time	5.426
Data Required Time	10.713
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.426	2.549	tNET	FF	16	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					MIPI_CLK_RX_P
10.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
10.682	0.683	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
10.682	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.865	0.182	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.865	0.000	tNET	RR	1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/FCLK
10.830	-0.035	tUnc
10.713	-0.117	tSu		1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2

Path Statistics:

Clock Skew	-1.645
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.549, 87.398%; tC2Q: 0.368, 12.602%
Required Clock Path Delay	cell: 0.864, 100.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	5.287
Data Arrival Time	5.426
Data Required Time	10.713
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.683	0.683	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
2.509	1.827	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
2.877	0.368	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
5.426	2.549	tNET	FF	16	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					MIPI_CLK_RX_P
10.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
10.682	0.683	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
10.682	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
10.865	0.182	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
10.865	0.000	tNET	RR	1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/FCLK
10.830	-0.035	tUnc
10.713	-0.117	tSu		1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0

Path Statistics:

Clock Skew	-1.645
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.683, 27.198%; route: 1.827, 72.802%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.549, 87.398%; tC2Q: 0.368, 12.602%
Required Clock Path Delay	cell: 0.864, 100.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	2.729
Data Arrival Time	9.383
Data Required Time	12.112
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.383	1.770	tNET	FF	1	R21C43[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.460	1.793	tNET	RR	1	R21C43[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.112	-0.347	tSu		1	R21C43[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.770, 80.000%; tC2Q: 0.442, 20.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.793, 100.000%

Path19

Path Summary:

Slack	2.729
Data Arrival Time	9.383
Data Required Time	12.112
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.383	1.770	tNET	FF	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.460	1.793	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
12.112	-0.347	tSu		1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.770, 80.000%; tC2Q: 0.442, 20.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.793, 100.000%

Path20

Path Summary:

Slack	2.729
Data Arrival Time	9.383
Data Required Time	12.112
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.383	1.770	tNET	FF	1	R21C43[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.460	1.793	tNET	RR	1	R21C43[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
12.112	-0.347	tSu		1	R21C43[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.770, 80.000%; tC2Q: 0.442, 20.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.793, 100.000%

Path21

Path Summary:

Slack	2.729
Data Arrival Time	9.383
Data Required Time	12.112
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.383	1.770	tNET	FF	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.460	1.793	tNET	RR	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
12.112	-0.347	tSu		1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.045
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.770, 80.000%; tC2Q: 0.442, 20.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.793, 100.000%

Path22

Path Summary:

Slack	2.732
Data Arrival Time	9.383
Data Required Time	12.115
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.383	1.770	tNET	FF	1	R20C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.462	1.795	tNET	RR	1	R20C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
12.115	-0.347	tSu		1	R20C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.042
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.770, 80.000%; tC2Q: 0.442, 20.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.795, 100.000%

Path23

Path Summary:

Slack	2.798
Data Arrival Time	9.280
Data Required Time	12.078
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.280	1.668	tNET	FF	1	R17C43[2][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.426	1.759	tNET	RR	1	R17C43[2][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
12.078	-0.347	tSu		1	R17C43[2][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.078
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.668, 79.028%; tC2Q: 0.442, 20.972%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.759, 100.000%

Path24

Path Summary:

Slack	2.804
Data Arrival Time	9.289
Data Required Time	12.093
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.289	1.676	tNET	FF	1	R15C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.441	1.774	tNET	RR	1	R15C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.093	-0.347	tSu		1	R15C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.063
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.676, 79.115%; tC2Q: 0.442, 20.885%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.774, 100.000%

Path25

Path Summary:

Slack	2.804
Data Arrival Time	9.289
Data Required Time	12.093
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk_byte_out:[F]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.333	5.333					active clock edge time
5.333	0.000					clk_byte_out
5.333	0.000	tCL	FF	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.170	1.837	tNET	FF	1	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
7.613	0.442	tC2Q	FF	54	R24C36[0][B]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.289	1.676	tNET	FF	1	R15C41[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.667	10.667					active clock edge time
10.667	0.000					clk_byte_out
10.667	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
12.441	1.774	tNET	RR	1	R15C41[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
12.093	-0.347	tSu		1	R15C41[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.063
Setup Relationship	5.334
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.837, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.676, 79.115%; tC2Q: 0.442, 20.885%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.774, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.554
Data Arrival Time	2.936
Data Required Time	1.383
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.936	1.377	tNET	RR	1	R30C31[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
1.401	0.725	tNET	RR	1	R30C31[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK
1.436	0.035	tUnc
1.383	-0.053	tHld		1	R30C31[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.377, 90.533%; tC2Q: 0.144, 9.467%
Required Clock Path Delay	cell: 0.675, 48.233%; route: 0.725, 51.767%

Path2

Path Summary:

Slack	1.554
Data Arrival Time	2.936
Data Required Time	1.383
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.936	1.377	tNET	RR	1	R30C31[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
1.401	0.725	tNET	RR	1	R30C31[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK
1.436	0.035	tUnc
1.383	-0.053	tHld		1	R30C31[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.377, 90.533%; tC2Q: 0.144, 9.467%
Required Clock Path Delay	cell: 0.675, 48.233%; route: 0.725, 51.767%

Path3

Path Summary:

Slack	1.554
Data Arrival Time	2.936
Data Required Time	1.383
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.936	1.377	tNET	RR	1	R30C31[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
1.401	0.725	tNET	RR	1	R30C31[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK
1.436	0.035	tUnc
1.383	-0.053	tHld		1	R30C31[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.377, 90.533%; tC2Q: 0.144, 9.467%
Required Clock Path Delay	cell: 0.675, 48.233%; route: 0.725, 51.767%

Path4

Path Summary:

Slack	1.554
Data Arrival Time	2.936
Data Required Time	1.383
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.936	1.377	tNET	RR	1	R30C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
1.401	0.725	tNET	RR	1	R30C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK
1.436	0.035	tUnc
1.383	-0.053	tHld		1	R30C31[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0

Path Statistics:

Clock Skew	-0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.377, 90.533%; tC2Q: 0.144, 9.467%
Required Clock Path Delay	cell: 0.675, 48.233%; route: 0.725, 51.767%

Path5

Path Summary:

Slack	1.961
Data Arrival Time	2.937
Data Required Time	0.977
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.937	1.378	tNET	RR	16	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
0.675	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.831	0.156	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.831	0.000	tNET	RR	1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0/FCLK
0.867	0.035	tUnc
0.977	0.110	tHld		1	IOB14[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_0

Path Statistics:

Clock Skew	-0.583
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.378, 90.539%; tC2Q: 0.144, 9.461%
Required Clock Path Delay	cell: 0.831, 100.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	1.961
Data Arrival Time	2.937
Data Required Time	0.977
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.937	1.378	tNET	RR	16	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
0.675	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.831	0.156	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.831	0.000	tNET	RR	1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2/FCLK
0.867	0.035	tUnc
0.977	0.110	tHld		1	IOB18[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_2

Path Statistics:

Clock Skew	-0.583
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.378, 90.539%; tC2Q: 0.144, 9.461%
Required Clock Path Delay	cell: 0.831, 100.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	1.969
Data Arrival Time	2.945
Data Required Time	0.977
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.945	1.386	tNET	RR	16	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
0.675	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.831	0.156	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.831	0.000	tNET	RR	1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1/FCLK
0.867	0.035	tUnc
0.977	0.110	tHld		1	IOB16[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_1

Path Statistics:

Clock Skew	-0.583
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.386, 90.588%; tC2Q: 0.144, 9.412%
Required Clock Path Delay	cell: 0.831, 100.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	1.969
Data Arrival Time	2.945
Data Required Time	0.977
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.559	0.144	tC2Q	RR	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.945	1.386	tNET	RR	16	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
0.675	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.831	0.156	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.831	0.000	tNET	RR	1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3/FCLK
0.867	0.035	tUnc
0.977	0.110	tHld		1	IOB20[A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst4_IDES16_3

Path Statistics:

Clock Skew	-0.583
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.386, 90.588%; tC2Q: 0.144, 9.412%
Required Clock Path Delay	cell: 0.831, 100.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	2.008
Data Arrival Time	2.884
Data Required Time	0.877
From	Gowin_PLL_inst/u_pll_init/rLockOut_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV
Launch Clk	clkx2x4:[R]
Latch Clk	MIPI_CLK_RX_P:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clkx2x4
0.000	0.000	tCL	RR	1	IOB24[A]	clkx2x4_ibuf/I
0.675	0.675	tINS	RR	123	IOB24[A]	clkx2x4_ibuf/O
1.415	0.739	tNET	RR	1	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/CLK
1.556	0.141	tC2Q	RF	218	R35C34[1][A]	Gowin_PLL_inst/u_pll_init/rLockOut_s0/Q
2.884	1.328	tNET	FF	1	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/RESETN

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MIPI_CLK_RX_P
0.000	0.000	tCL	RR	3	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO
0.675	0.675	tINS	RR	5	IOB22	MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH
0.675	0.000	tNET	RR	3	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN
0.831	0.156	tINS	RR	5	R42C29	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKOUT
0.831	0.000	tNET	RR	5	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/HCLKIN
0.867	0.035	tUnc
0.877	0.010	tHld		1	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV

Path Statistics:

Clock Skew	-0.583
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 47.739%; route: 0.739, 52.261%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.328, 90.402%; tC2Q: 0.141, 9.598%
Required Clock Path Delay	cell: 0.831, 100.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_1_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R11C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_1_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R11C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_1_13_s0/CLK
0.667	-0.053	tHld		1	R11C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_1_13_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path11

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_0_13_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R11C28[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_0_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R11C28[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_0_13_s0/CLK
0.667	-0.053	tHld		1	R11C28[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in3_0_13_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path12

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_7_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R29C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R29C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_7_s0/CLK
0.667	-0.053	tHld		1	R29C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_7_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path13

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R11C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R11C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0/CLK
0.667	-0.053	tHld		1	R11C24[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_3_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path14

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_1_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R11C24[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R11C24[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_1_s0/CLK
0.667	-0.053	tHld		1	R11C24[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/shftamt_1_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path15

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg3_1_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R11C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg3_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R11C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg3_1_s0/CLK
0.667	-0.053	tHld		1	R11C28[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg3_1_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path16

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R29C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R29C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0/CLK
0.667	-0.053	tHld		1	R29C28[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_6_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path17

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R29C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R29C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0/CLK
0.667	-0.053	tHld		1	R29C28[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/shftamt_5_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path18

Path Summary:

Slack	2.523
Data Arrival Time	3.190
Data Required Time	0.667
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_5_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.190	1.202	tNET	RR	1	R29C24[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.720	0.720	tNET	RR	1	R29C24[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_5_s0/CLK
0.667	-0.053	tHld		1	R29C24[0][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd2/reg2_5_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.404%; route: 1.928, 77.899%; tC2Q: 0.141, 5.697%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.720, 100.000%

Path19

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R29C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R29C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_3_s0/CLK
0.671	-0.053	tHld		1	R29C29[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in2_0_3_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path20

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_1_14_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R29C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_1_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R29C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_1_14_s0/CLK
0.671	-0.053	tHld		1	R29C17[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_1_14_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path21

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_5_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R29C13[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R29C13[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_5_s0/CLK
0.671	-0.053	tHld		1	R29C13[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_5_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path22

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_14_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R29C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R29C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_14_s0/CLK
0.671	-0.053	tHld		1	R29C17[0][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/ln0/q_in0_0_14_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path23

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R11C25[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R11C25[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_3_s0/CLK
0.671	-0.053	tHld		1	R11C25[2][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_3_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path24

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_6_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R11C25[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R11C25[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_6_s0/CLK
0.671	-0.053	tHld		1	R11C25[1][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg4_6_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Path25

Path Summary:

Slack	2.523
Data Arrival Time	3.194
Data Required Time	0.671
From	rx_hs_en_mask_s0
To	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg2_3_s0
Launch Clk	clk_byte_out:[R]
Latch Clk	clk_byte_out:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.715	0.715	tNET	RR	1	R32C31[1][A]	rx_hs_en_mask_s0/CLK
0.856	0.141	tC2Q	RF	2	R32C31[1][A]	rx_hs_en_mask_s0/Q
0.925	0.069	tNET	FF	1	R32C31[3][B]	n206_s0/I0
1.185	0.260	tINS	FR	6	R32C31[3][B]	n206_s0/F
1.842	0.657	tNET	RR	1	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/I0
1.988	0.146	tINS	RR	737	R34C18[1][A]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd0/n38_s1/F
3.194	1.206	tNET	RR	1	R11C25[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg2_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_byte_out
0.000	0.000	tCL	RR	1239	BOTTOMSIDE[2]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
0.724	0.724	tNET	RR	1	R11C25[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg2_3_s0/CLK
0.671	-0.053	tHld		1	R11C25[2][B]	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/wd3/reg2_3_s0

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.715, 100.000%
Arrival Data Path Delay	cell: 0.406, 16.378%; route: 1.932, 77.935%; tC2Q: 0.141, 5.688%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.724, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.241
Actual Width:	4.241
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.155	1.822	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.396	0.729	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW2

MPW Summary:

Slack:	3.241
Actual Width:	4.241
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.155	1.822	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.396	0.729	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

MPW3

MPW Summary:

Slack:	3.246
Actual Width:	4.246
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.146	1.813	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.392	0.725	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW4

MPW Summary:

Slack:	3.246
Actual Width:	4.246
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.146	1.813	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.392	0.725	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA

MPW5

MPW Summary:

Slack:	3.246
Actual Width:	4.246
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.146	1.813	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.392	0.725	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA

MPW6

MPW Summary:

Slack:	3.246
Actual Width:	4.246
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.146	1.813	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.392	0.725	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA

MPW7

MPW Summary:

Slack:	3.252
Actual Width:	4.252
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
7.136	1.803	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.667	0.000			active clock edge time
10.667	0.000			clk_byte_out
10.667	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
11.388	0.721	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW8

MPW Summary:

Slack:	3.303
Actual Width:	4.303
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_byte_out
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.780	1.780	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
6.083	0.750	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA

MPW9

MPW Summary:

Slack:	3.303
Actual Width:	4.303
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_byte_out
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.780	1.780	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
6.083	0.750	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA

MPW10

MPW Summary:

Slack:	3.308
Actual Width:	4.308
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk_byte_out
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk_byte_out
0.000	0.000	tCL	RR	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
1.770	1.770	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.333	0.000			active clock edge time
5.333	0.000			clk_byte_out
5.333	0.000	tCL	FF	MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT
6.079	0.746	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
1239	clk_byte_out	3.798	1.858
737	MIPI_RX_Advance_Top/DPHY_RX_INST/u_Aligner/n38_5	5.150	2.528
407	gw_gao_inst_0/control0[0]	18.460	3.124
218	rLockOut	4.950	2.958
133	gw_gao_inst_0/u_la0_top/n20_3	45.902	1.974
123	clkx2x4_d	0.279	2.501
113	gw_gao_inst_0/u_la0_top/data_out_shift_reg_110_7	43.624	2.782
111	gw_gao_inst_0/u_la0_top/n1087_5	44.242	1.830
96	gw_gao_inst_0/u_la0_top/n1087_4	43.636	2.455
77	ready	8.308	1.531

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C4	100.00%
R2C8	100.00%
R2C16	100.00%
R2C32	100.00%
R3C10	100.00%
R4C20	100.00%
R12C15	100.00%
R12C16	100.00%
R22C20	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_byte_out -period 10.667 -waveform {0 5.333} [get_nets {clk_byte_out}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK	Actived	create_clock -name MIPI_CLK_RX_P -period 10 -waveform {0 5} [get_ports {MIPI_CLK_RX_P}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {MIPI_CLK_RX_P}] -to [get_clocks {MIPI_CLK_RX_P}]