Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\DPHY_TOP.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\dphy_tx_fifo\dphy_tx_fifo.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\gowin_pll\gowin_pll_mod.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\mipi_rx_advance\mipi_rx_advance.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\mipi_tx_advance\mipi_tx_advance.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\pll_init.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\src\tx_pattern_gen.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.12_x64\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\version\1.9.12\Gowin_MIPI_DPHY_Advance_refDesign\MIPI_RefDesign_5a15_MIPI_IO\MIPI_RefDesign\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW5ART-LV15MG132PC1/I0 |
| Device | GW5ART-15 |
| Device Version | A |
| Created Time | Tue Aug 26 16:40:50 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DPHY_TOP |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.952s, Peak memory usage = 805.227MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.472s, Peak memory usage = 805.227MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 805.227MB Optimizing Phase 2: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.509s, Peak memory usage = 805.227MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.222s, Peak memory usage = 805.227MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 805.227MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 805.227MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 805.227MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.173s, Peak memory usage = 805.227MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 805.227MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 805.227MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 805.227MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 805.227MB Generate output files: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 805.227MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 805.227MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 25 |
| I/O Buf | 10 |
| IBUF | 4 |
| OBUF | 1 |
| MIPI_IBUF | 5 |
| Register | 1753 |
| DFFSE | 1 |
| DFFRE | 121 |
| DFFPE | 46 |
| DFFCE | 1585 |
| LUT | 2299 |
| LUT2 | 251 |
| LUT3 | 425 |
| LUT4 | 1623 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 155 |
| ALU | 155 |
| ROM16 | 60 |
| ROM16 | 60 |
| INV | 19 |
| INV | 19 |
| IOLOGIC | 8 |
| IDES16 | 4 |
| IODELAY | 4 |
| BSRAM | 7 |
| SDPB | 7 |
| CLOCK | 3 |
| CLKDIV | 1 |
| DHCE | 1 |
| PLLA | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2541(2326 LUT, 155 ALU, 60 ROM16) / 15120 | 17% |
| Register | 1753 / 15231 | 12% |
| --Register as Latch | 0 / 15231 | 0% |
| --Register as FF | 1753 / 15231 | 12% |
| BSRAM | 7 / 35 | 20% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clkx2x4 | Base | 20.000 | 50.000 | 0.000 | 10.000 | clkx2x4_ibuf/I | ||
| 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | Base | 10.000 | 100.000 | 0.000 | 5.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | ||
| 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | Generated | 80.000 | 12.500 | 0.000 | 40.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clkx2x4 | 50.000(MHz) | 184.374(MHz) | 7 | TOP |
| 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | 100.000(MHz) | 277.662(MHz) | 2 | TOP |
| 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | 12.500(MHz) | 187.705(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.199 |
| Data Arrival Time | 1.969 |
| Data Required Time | 5.168 |
| From | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
| To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN |
| Launch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[F] |
| Latch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 0.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 0.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 0.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/I2 |
| 1.594 | 0.461 | tINS | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_0/F |
| 1.969 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 5.000 | 0.000 | tCL | FF | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 5.000 | 0.000 | tINS | FF | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 5.350 | 0.350 | tNET | FF | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN |
| 5.168 | -0.182 | tSu | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/u_DHCEN |
| Clock Skew: | -0.025 |
| Setup Relationship: | 5.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 8.095 |
| Data Arrival Time | 1.969 |
| Data Required Time | 10.064 |
| From | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
| To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
| Launch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| Latch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 0.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 0.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 0.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
| 1.594 | 0.461 | tINS | RR | 4 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F |
| 1.969 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 10.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 10.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 10.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0/CLK |
| 10.064 | -0.311 | tSu | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 8.095 |
| Data Arrival Time | 1.969 |
| Data Required Time | 10.064 |
| From | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
| To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
| Launch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| Latch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 0.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 0.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 0.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
| 1.594 | 0.461 | tINS | RR | 4 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F |
| 1.969 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 10.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 10.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 10.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
| 10.064 | -0.311 | tSu | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 8.095 |
| Data Arrival Time | 1.969 |
| Data Required Time | 10.064 |
| From | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
| To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
| Launch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| Latch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 0.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 0.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 0.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
| 1.594 | 0.461 | tINS | RR | 4 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F |
| 1.969 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 10.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 10.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 10.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
| 10.064 | -0.311 | tSu | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 8.095 |
| Data Arrival Time | 1.969 |
| Data Required Time | 10.064 |
| From | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0 |
| To | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
| Launch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| Latch Clk | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 0.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 0.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 0.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 2 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_3_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/I2 |
| 1.594 | 0.461 | tINS | RR | 4 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/LUT4_1/F |
| 1.969 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO | |||
| 10.000 | 0.000 | tCL | RR | 3 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/IO |
| 10.000 | 0.000 | tINS | RR | 5 | MIPI_RX_Advance_Top/DPHY_RX_INST/MIPI_IBUF_CLK/OH |
| 10.375 | 0.375 | tNET | RR | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0/CLK |
| 10.064 | -0.311 | tSu | 1 | MIPI_RX_Advance_Top/DPHY_RX_INST/u_idesx8/opensync_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.461, 28.941%; route: 0.750, 47.059%; tC2Q: 0.382, 24.000% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |