Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\UARTMASTER\data\uart_master_top.v C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\UARTMASTER\data\uart_master_encrypt.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.01 |
| Part Number | GW1N-LV4LQ144C6/I5 |
| Device | GW1N-4B |
| Created Time | Mon Nov 01 15:14:57 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | UART_MASTER_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.227s, Peak memory usage = 43.387MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 43.387MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 43.387MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 43.387MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 43.387MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 43.387MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.387MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.387MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.387MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 43.387MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 43.387MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 43.387MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.55s, Peak memory usage = 54.484MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 54.484MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 54.484MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.932s, Elapsed time = 0h 0m 0.959s, Peak memory usage = 54.484MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 38 |
| I/O Buf | 38 |
| IBUF | 23 |
| OBUF | 15 |
| Register | 209 |
| DFFS | 2 |
| DFFR | 3 |
| DFFP | 11 |
| DFFPE | 11 |
| DFFC | 116 |
| DFFCE | 64 |
| DFFNP | 2 |
| LUT | 219 |
| LUT2 | 52 |
| LUT3 | 67 |
| LUT4 | 100 |
| ALU | 28 |
| ALU | 28 |
| INV | 11 |
| INV | 11 |
| BSRAM | 2 |
| SDPB | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 258(230 LUTs, 28 ALUs) / 4608 | 6% |
| Register | 209 / 3756 | 6% |
| --Register as Latch | 0 / 3756 | 0% |
| --Register as FF | 209 / 3756 | 6% |
| BSRAM | 2 / 10 | 20% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_CLK | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_CLK_ibuf/I | ||
| rxclk_Z | Base | 20.000 | 50.0 | 0.000 | 10.000 | i4/u_baudset/rxclk_s1/Q |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_CLK | 50.0(MHz) | 105.3(MHz) | 7 | TOP |
| 2 | rxclk_Z | 50.0(MHz) | 168.3(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 10.505 |
| Data Arrival Time | 10.440 |
| Data Required Time | 20.945 |
| From | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0 |
| To | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 9 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/n27_s0/I1 |
| 3.382 | 1.099 | tINS | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/n27_s0/F |
| 3.862 | 0.480 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_0_s/I1 |
| 4.907 | 1.045 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_0_s/COUT |
| 4.907 | 0.000 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_1_s/CIN |
| 4.964 | 0.057 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_1_s/COUT |
| 4.964 | 0.000 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_2_s/CIN |
| 5.021 | 0.057 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_2_s/COUT |
| 5.021 | 0.000 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_3_s/CIN |
| 5.078 | 0.057 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_3_s/COUT |
| 5.078 | 0.000 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_4_s/CIN |
| 5.641 | 0.563 | tINS | FF | 3 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rbin_num_next_4_s/SUM |
| 6.121 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.rgraynext_3_s0/I1 |
| 7.220 | 1.099 | tINS | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.rgraynext_3_s0/F |
| 7.700 | 0.480 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/n80_s0/I0 |
| 8.658 | 0.958 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/n80_s0/COUT |
| 9.138 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rempty_val_s1/I2 |
| 9.960 | 0.822 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/rempty_val_s1/F |
| 10.440 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_CLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.757, 63.296%; route: 2.880, 31.665%; tC2Q: 0.458, 5.039% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:| Slack | 10.572 |
| Data Arrival Time | 10.373 |
| Data Required Time | 20.945 |
| From | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0 |
| To | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 3 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/n27_s0/I0 |
| 3.315 | 1.032 | tINS | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/n27_s0/F |
| 3.795 | 0.480 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_0_s/I1 |
| 4.840 | 1.045 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_0_s/COUT |
| 4.840 | 0.000 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_1_s/CIN |
| 4.897 | 0.057 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_1_s/COUT |
| 4.897 | 0.000 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_2_s/CIN |
| 4.954 | 0.057 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_2_s/COUT |
| 4.954 | 0.000 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_3_s/CIN |
| 5.011 | 0.057 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_3_s/COUT |
| 5.011 | 0.000 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_4_s/CIN |
| 5.574 | 0.563 | tINS | FF | 3 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rbin_num_next_4_s/SUM |
| 6.054 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.rgraynext_3_s0/I1 |
| 7.153 | 1.099 | tINS | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.rgraynext_3_s0/F |
| 7.633 | 0.480 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/n80_s0/I0 |
| 8.591 | 0.958 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/n80_s0/COUT |
| 9.071 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rempty_val_s1/I2 |
| 9.893 | 0.822 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/rempty_val_s1/F |
| 10.373 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_CLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.690, 63.023%; route: 2.880, 31.900%; tC2Q: 0.458, 5.077% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:| Slack | 10.602 |
| Data Arrival Time | 10.343 |
| Data Required Time | 20.945 |
| From | i4/u_uart_sram/ThrWRn_re_s0 |
| To | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Full_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | i4/u_uart_sram/ThrWRn_re_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 3 | i4/u_uart_sram/ThrWRn_re_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/fifo_wr_s1/I1 |
| 3.382 | 1.099 | tINS | FF | 2 | i4/U_Txmitt/fifo_wr_s1/F |
| 3.862 | 0.480 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.wbinnext_0_s/I1 |
| 4.907 | 1.045 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.wbinnext_0_s/COUT |
| 4.907 | 0.000 | tNET | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.wbinnext_1_s/CIN |
| 5.470 | 0.563 | tINS | FF | 3 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.wbinnext_1_s/SUM |
| 5.950 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.wgraynext_0_s0/I0 |
| 6.982 | 1.032 | tINS | FF | 2 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Equal.wgraynext_0_s0/F |
| 7.462 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/wfull_val_s1/I1 |
| 8.561 | 1.099 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/wfull_val_s1/F |
| 9.041 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/wfull_val_s0/I2 |
| 9.863 | 0.822 | tINS | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/wfull_val_s0/F |
| 10.343 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_CLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Full_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | i4/U_Txmitt/Tx_FIFO/u_uart_fifo/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.660, 62.900%; route: 2.880, 32.006%; tC2Q: 0.458, 5.094% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:| Slack | 10.602 |
| Data Arrival Time | 10.343 |
| Data Required Time | 20.945 |
| From | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0 |
| To | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0 |
| Launch Clk | I_CLK[R] |
| Latch Clk | I_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/n23_s1/I1 |
| 3.382 | 1.099 | tINS | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/n23_s1/F |
| 3.862 | 0.480 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.wbinnext_0_s/I1 |
| 4.907 | 1.045 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.wbinnext_0_s/COUT |
| 4.907 | 0.000 | tNET | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.wbinnext_1_s/CIN |
| 5.470 | 0.563 | tINS | FF | 3 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.wbinnext_1_s/SUM |
| 5.950 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.wgraynext_0_s0/I0 |
| 6.982 | 1.032 | tINS | FF | 2 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Equal.wgraynext_0_s0/F |
| 7.462 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/wfull_val_s1/I1 |
| 8.561 | 1.099 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/wfull_val_s1/F |
| 9.041 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/wfull_val_s0/I2 |
| 9.863 | 0.822 | tINS | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/wfull_val_s0/F |
| 10.343 | 0.480 | tNET | FF | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_CLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | i4/U_Rxcver/Rx_FIFO/u_uart_fifo/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.660, 62.900%; route: 2.880, 32.006%; tC2Q: 0.458, 5.094% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:| Slack | 13.047 |
| Data Arrival Time | 6.886 |
| Data Required Time | 19.933 |
| From | i4/u_uart_sram/LCR_4_s0 |
| To | i4/U_Txmitt/TxOutput_s1 |
| Launch Clk | I_CLK[R] |
| Latch Clk | rxclk_Z[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_CLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 163 | I_CLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | i4/u_uart_sram/LCR_4_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 3 | i4/u_uart_sram/LCR_4_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/n149_s12/I1 |
| 3.382 | 1.099 | tINS | FF | 1 | i4/U_Txmitt/n149_s12/F |
| 3.862 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/n149_s9/I0 |
| 4.894 | 1.032 | tINS | FF | 1 | i4/U_Txmitt/n149_s9/F |
| 5.374 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/n149_s8/I0 |
| 6.406 | 1.032 | tINS | FF | 1 | i4/U_Txmitt/n149_s8/F |
| 6.886 | 0.480 | tNET | FF | 1 | i4/U_Txmitt/TxOutput_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | rxclk_Z | |||
| 20.000 | 0.000 | tCL | RR | 50 | i4/u_baudset/rxclk_s1/Q |
| 20.363 | 0.363 | tNET | RR | 1 | i4/U_Txmitt/TxOutput_s1/CLK |
| 20.333 | -0.030 | tUnc | i4/U_Txmitt/TxOutput_s1 | ||
| 19.933 | -0.400 | tSu | 1 | i4/U_Txmitt/TxOutput_s1 |
| Clock Skew: | -0.982 |
| Setup Relationship: | 20.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 3.163, 57.080%; route: 1.920, 34.649%; tC2Q: 0.458, 8.271% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |