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         GOWIN UART MASTER IP参考设计阅读指南
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目标器件：GW1N-LV4LQ144C6/I5
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文件列表
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.
|-- doc
|   `-- readme.txt                          -->  自述文件
|-- tb 
|   `-- uart_tb.v                           -->  GOWIN UART参考设计仿真TestBench文件
|-- simulation
|   |-- Modelsim
|       `-- cmd.do			    -->	 Modelsim仿真脚本
|-- simlib
|   |-- gw1n
|   |   `-- prim_sim.v                      -->  GOWIN GW1N系列FPGA仿真库文件
|   |-- gw2a
|       `-- prim_sim.v                      -->  GOWIN GW2A系列FPGA仿真库文件
|-- simulate_vo
|   `-- gw_uart_slave.vo                    -->  GOWIN UART Slave参考设计仿真模型
|-- project
    |-- gw_uart_master
    |        |  `-- gw_uart_master.gprj     -->  GOWIN UART MASTER IP参考设计工程
    |        |-- impl
    |        |-- src 
    |            |-- gowin_rpll             -->  参考设计IP文件夹
    |            |-- uart_master            -->  参考设计IP文件夹
    |            `-- gw_uart_master.cst     -->  参考设计工程文件
    |            `-- gw_uart_master.rao     -->  参考设计工程文件
    |            `-- gw_uart_master.sdc     -->  参考设计工程文件
    |            `-- gw_uart_master.v       -->  参考设计工程文件
    |            `-- master_sram_uart.v     -->  参考设计工程文件
    |-- gw_uart_slave
             |  `-- gw_uart_slave.gprj      -->  GOWIN UART SLAVE参考设计工程
             |-- impl
             |-- src 
                 `-- gw_uart_slave.cst      -->  参考设计工程文件
                 `-- gw_uart_slave.rao      -->  参考设计工程文件
                 `-- gw_uart_slave.sdc      -->  参考设计工程文件
                 `-- gw_uart_slave.v        -->  参考设计工程文件
                 `-- uart_slave.v           -->  参考设计工程文件
                 `-- uart_slave_defines.vh  -->  参考设计工程文件

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如何在云源软件里打开工程：
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1. 解压已压缩的设计文件。
2. 启动云源软件并选择“File -> Open”。
3. 在已打开的“Open File”窗口中进入对应工程所在路径，选择工程文件“gw_uart_master.gprj”。
4. 点击“打开”，则工程即可加载。 

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如何在云源软件中运行综合，布局布线及时序分析：
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1. 点击云源软件界面中Process面板中的Process选项卡，双击Synthsize(GowinSynthesis)，这将使设计运行综合。
2. 点击”Project -> Configuration -> Place & Route”以设置生成Post-place文件及SDF文件等。
3. 点击云源软件界面中Process面板中的Process选项卡，双击Place & Route，这将使设计运行映射及布局布线。
4. 当布局布线完成时，用户可以双击Timing Analysis Report得到时序分析结果。

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如何运行工程仿真：
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1. 启动Modelsim并点击change directory至路径“../Gowin_UART_Master_RefDesign/simulation/Modelsim”。 
2. 在transcript window中执行脚本文件（cmd.do）。
3. 在Modelsim软件中查看仿真波形。



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	  GOWIN UART MASTER IP Design Example Readme
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Object device: GW1N-LV4LQ144C6/I5
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File List:
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.
|-- doc
|   `-- readme.txt                          -->  Read Me file (this file)
|-- tb 
|   `-- uart_tb.v                           -->  TestBench for GOWIN UART Ref design
|-- simulation
|   |-- Modelsim
|       `-- cmd.do			    -->	 Modelsim simulation script
|-- simlib
|   |-- gw1n
|   |   `-- prim_sim.v                      -->  GOWIN GW1N FPGA simulation library file
|   |-- gw2a
|       `-- prim_sim.v                      -->  GOWIN GW2A FPGA simulation library file
|-- simulate_vo
|   `-- gw_uart_slave.vo                    -->  GOWIN UART Slave Example Design simulation model
|-- project
    |-- gw_uart_master
    |        |  `-- gw_uart_master.gprj     -->  Project for GOWIN UART MASTER IP Design Example
    |        |-- impl
    |        |-- src 
    |            |-- gowin_rpll             -->  Design Example Project IP File folder
    |            |-- uart_master            -->  Design Example Project IP File folder
    |            `-- gw_uart_master.cst     -->  Design Example Project File
    |            `-- gw_uart_master.rao     -->  Design Example Project File
    |            `-- gw_uart_master.sdc     -->  Design Example Project File
    |            `-- gw_uart_master.v       -->  Design Example Project File
    |            `-- master_sram_uart.v     -->  Design Example Project File
    |-- gw_uart_slave
             |  `-- gw_uart_slave.gprj      -->  Project for GOWIN UART SLAVE Design Example
             |-- impl
             |-- src 
                 `-- gw_uart_slave.cst      -->  Design Example Project File
                 `-- gw_uart_slave.rao      -->  Design Example Project File
                 `-- gw_uart_slave.sdc      -->  Design Example Project File
                 `-- gw_uart_slave.v        -->  Design Example Project File
                 `-- uart_slave.v           -->  Design Example Project File
                 `-- uart_slave_defines.vh  -->  Design Example Project File

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HOW TO OPEN A PROJECT IN GOWIN EDA:
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1. Unzip the compressed design files.
2. Start the GOWIN EDA and select "File -> Open"
3. In the Open File dialog, enter the Project location, select the project "gw_uart_master.gprj".
4. Click "Open". Then the project could be loaded. 

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HOW TO RUN SYNTHESIZE, PLACE&ROUTE AND TIMING ANALYSIS IN GOWIN EDA:
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1. Click the Process tab in the process panel of the GOWIN EDA dashboard. 
   Double click on Synthsize(GowinSynthesis). This will bring the design through synthesis.
2. Click on "Project -> Configuration -> Place & Route" to configurate the generation of the Post-Place File 
   and SDF File,etc.
3. Click the Process tab in the process panel of the GOWIN EDA dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
4. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.

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HOW TO RUN SIMULATION
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1. Start the Modelsim and change directory to "../Gowin_UART_Master_RefDesign/simulation/Modelsim". 
2. Run the script(cmd.do) in the transcript window.
3. Check waveform by software Modelsim.