@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT529 :"d:\ip release\spi_sram\gowin_spi_refdesign_for_release_190917\gowin_spi_slave_refdesign\project\gw_spi_slave\src\spi_slave.v":94:4:94:9|Found inferred clock gw_spi_slave|SCLK which controls 25 sequential elements including u_spi_slave.genblk2\.miso_shift_reg[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
