@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "00000000" on instance u_spi_slave.genblk2\.miso_shift_reg[7:0].
@N: FX493 |Applying initial value "000" on instance u_spi_slave.genblk2\.tx_cnt[2:0].
@N: FX493 |Applying initial value "00000000" on instance u_spi_slave.genblk1\.mosi_shift_reg[7:0].
@N: FX493 |Applying initial value "000000" on instance u_spi_slave.genblk1\.rx_cnt[5:0].
@N: FX271 :"d:\ip release\spi_sram\gowin_spi_refdesign_for_release_190917\gowin_spi_slave_refdesign\project\gw_spi_slave\src\spi_slave.v":45:4:45:9|Replicating instance u_spi_slave.genblk1\.rx_cnt[0] (in view: work.gw_spi_slave(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\ip release\spi_sram\gowin_spi_refdesign_for_release_190917\gowin_spi_slave_refdesign\project\gw_spi_slave\src\spi_slave.v":45:4:45:9|Replicating instance u_spi_slave.genblk1\.rx_cnt[1] (in view: work.gw_spi_slave(verilog)) with 4 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
