Project Settings
Project Name SPI_MASTER Device Name rev_1: GOWIN-GW1N : GW1N_4B
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 1 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 8 0 0 - 00m:00s - 2019/9/18
11:00:41
(premap)Complete 9 0 0 0m:01s 0m:01s 191MB 2019/9/18
11:00:45
(fpga_mapper)Complete 11 1 0 0m:03s 0m:03s 196MB 2019/9/18
11:00:49
Multi-srs Generator Complete00m:01s2019/9/18
11:00:43

Area Summary
Non I/O Register bits (non_io_reg) 79 (2%) I/O Register bits (total_io_reg) 0
Block Rams (v_ram) 0 (10) Block Multipliers (dsp_used) 0 (8)
LUTs (total_luts) 128 (2%)

Timing Summary
Clock NameReq FreqEst FreqSlack
SPI_MASTER_Top|I_CLK100.0 MHz84.5 MHz-1.833
System100.0 MHz866.6 MHz8.846

Optimizations Summary
Combined Clock Conversion 1 / 0