#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: Desktop-2019KKU # Wed Sep 18 11:00:41 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\spi_master_top.v" (library work) @I:"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\spi_master_top.v":"D:\spi_master\project\gw_spi_master\src\spi_master\temp\SPI_MASTER\top_define.vh" (library work) @I:"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\spi_master_top.v":"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\static_macro_define.vh" (library work) @I:"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\spi_master_top.v":"D:\spi_master\project\gw_spi_master\src\spi_master\temp\SPI_MASTER\spi_master_defines.vh" (library work) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\spi_master.vp" (library work) Verilog syntax check successful! Selecting top level module SPI_MASTER_Top Running optimization stage 1 on \~spi_master.SPI_MASTER_Top ....... @N:CG364 : spi_master_top.v(5) | Synthesizing module SPI_MASTER_Top in library work. Running optimization stage 1 on SPI_MASTER_Top ....... Running optimization stage 2 on SPI_MASTER_Top ....... Running optimization stage 2 on \~spi_master.SPI_MASTER_Top ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 11:00:41 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:NF107 : spi_master_top.v(5) | Selected library: work cell: SPI_MASTER_Top view verilog as top level @N:NF107 : spi_master_top.v(5) | Selected library: work cell: SPI_MASTER_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 11:00:41 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 11:00:41 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:NF107 : spi_master_top.v(5) | Selected library: work cell: SPI_MASTER_Top view verilog as top level @N:NF107 : spi_master_top.v(5) | Selected library: work cell: SPI_MASTER_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 11:00:43 2019 ###########################################################] Premap Report # Wed Sep 18 11:00:43 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: spi_master_scck.rpt Printing clock summary report in "D:\spi_master\project\gw_spi_master\src\spi_master\temp\SPI_MASTER\rev_1\spi_master_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------- 0 - SPI_MASTER_Top|I_CLK 120.0 MHz 8.336 inferred Autoconstr_clkgroup_0 72 =========================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------- SPI_MASTER_Top|I_CLK 72 I_CLK(port) u_spi_master.reg_ssmask[0].C - - =================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 72 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 I_CLK Unconstrained_port 72 ENCRYPTED ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\spi_master\project\gw_spi_master\src\spi_master\temp\SPI_MASTER\rev_1\spi_master.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 191MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Sep 18 11:00:45 2019 ###########################################################] Map & Optimize Report # Wed Sep 18 11:00:45 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 191MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -4.05ns 112 / 72 2 0h:00m:01s -3.19ns 108 / 72 3 0h:00m:01s -2.94ns 108 / 72 4 0h:00m:01s -3.19ns 108 / 72 Timing driven replication report Added 3 Registers via timing driven replication Added 2 LUTs via timing driven replication 5 0h:00m:01s -2.62ns 110 / 75 6 0h:00m:01s -2.05ns 113 / 75 7 0h:00m:01s -1.51ns 116 / 75 8 0h:00m:01s -1.76ns 116 / 75 9 0h:00m:01s -1.82ns 118 / 75 10 0h:00m:01s -1.76ns 119 / 75 Timing driven replication report Added 4 Registers via timing driven replication Added 0 LUTs via timing driven replication 11 0h:00m:01s -1.45ns 130 / 79 12 0h:00m:01s -1.51ns 130 / 79 13 0h:00m:01s -1.51ns 131 / 79 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 123MB peak: 196MB) Writing Analyst data base D:\spi_master\project\gw_spi_master\src\spi_master\temp\SPI_MASTER\rev_1\synwork\spi_master_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 196MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 193MB peak: 196MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 194MB peak: 196MB) Warning: Found 3 combinational loops! 1) instance genblk1\.n_status_8_1_iv[2] (in view: work.\\\~spi_master\.SPI_MASTER_Top\ (verilog)), output net genblk1\.n_status_8_1_iv[2] (in view: work.\\\~spi_master\.SPI_MASTER_Top\ (verilog)) net u_spi_master.genblk1\.n_status_8_1_iv[2] input pin u_spi_master.genblk1\.n_status_8_1_iv_N_4L5/I0 instance u_spi_master.genblk1\.n_status_8_1_iv_N_4L5 (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_1_iv_N_4L5/F net u_spi_master.genblk1\.n_status_8_1_iv_1[2] input pin u_spi_master.genblk1\.n_status_8_1_iv[2]/I1 instance u_spi_master.genblk1\.n_status_8_1_iv[2] (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_1_iv[2]/F net u_spi_master.genblk1\.n_status_8_1_iv[2] 2) instance genblk1\.n_status_8_1_iv[0] (in view: work.\\\~spi_master\.SPI_MASTER_Top\ (verilog)), output net genblk1\.n_status_8_1_iv[0] (in view: work.\\\~spi_master\.SPI_MASTER_Top\ (verilog)) net u_spi_master.genblk1\.n_status_8_1_iv[0] input pin u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1/I1 instance u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1 (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1/F net u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1_0 input pin u_spi_master.genblk1\.n_status_8_1_iv_N_5L7/I1 instance u_spi_master.genblk1\.n_status_8_1_iv_N_5L7 (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_1_iv_N_5L7/F net u_spi_master.genblk1\.n_status_8_1_iv_N_5L7 input pin u_spi_master.genblk1\.n_status_8_1_iv[0]/I2 instance u_spi_master.genblk1\.n_status_8_1_iv[0] (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_1_iv[0]/F net u_spi_master.genblk1\.n_status_8_1_iv[0] 3) instance genblk1\.n_status_8_0_iv[1] (in view: work.\\\~spi_master\.SPI_MASTER_Top\ (verilog)), output net genblk1\.n_status_8_0_iv[1] (in view: work.\\\~spi_master\.SPI_MASTER_Top\ (verilog)) net u_spi_master.genblk1\.n_status_8_0_iv[1] input pin u_spi_master.genblk1\.n_status_8_0_iv_N_3L3/I1 instance u_spi_master.genblk1\.n_status_8_0_iv_N_3L3 (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_0_iv_N_3L3/F net u_spi_master.genblk1\.n_status_8_0_iv_1[1] input pin u_spi_master.genblk1\.n_status_8_0_iv[1]/I1 instance u_spi_master.genblk1\.n_status_8_0_iv[1] (cell LUT4) output pin u_spi_master.genblk1\.n_status_8_0_iv[1]/F net u_spi_master.genblk1\.n_status_8_0_iv[1] End of loops @W:MT420 : | Found inferred clock SPI_MASTER_Top|I_CLK with period 10.00ns. Please declare a user-defined clock on port I_CLK. ##### START OF TIMING REPORT #####[ # Timing report written on Wed Sep 18 11:00:48 2019 # Top view: SPI_MASTER_Top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.833 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------ SPI_MASTER_Top|I_CLK 100.0 MHz 84.5 MHz 10.000 11.833 -1.833 inferred Autoconstr_clkgroup_0 System 100.0 MHz 866.6 MHz 10.000 1.154 8.846 system system_clkgroup ============================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------- System SPI_MASTER_Top|I_CLK | 10.000 8.846 | No paths - | No paths - | No paths - SPI_MASTER_Top|I_CLK System | 10.000 8.612 | No paths - | No paths - | No paths - SPI_MASTER_Top|I_CLK SPI_MASTER_Top|I_CLK | 10.000 -1.833 | No paths - | No paths - | No paths - =================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SPI_MASTER_Top|I_CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------- u_spi_master.genblk1\.c_status_1_rep1 SPI_MASTER_Top|I_CLK DFFC Q genblk1\.c_status_1_rep1 0.367 -1.833 u_spi_master.genblk1\.c_status_0_rep1 SPI_MASTER_Top|I_CLK DFFC Q genblk1\.c_status_0_rep1 0.367 -1.766 u_spi_master.genblk1\.clock_cnt[3] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.clock_cnt[3] 0.367 -1.570 u_spi_master.genblk1\.clock_cnt[2] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.clock_cnt[2] 0.367 -1.556 u_spi_master.genblk1\.clock_cnt[1] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.clock_cnt[1] 0.367 -1.489 u_spi_master.genblk1\.data_cnt[4] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.data_cnt[4] 0.367 -1.376 u_spi_master.genblk1\.data_cnt[3] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.data_cnt[3] 0.367 -1.360 u_spi_master.genblk1\.clock_cnt[4] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.clock_cnt[4] 0.367 -1.293 u_spi_master.genblk1\.data_cnt[2] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.data_cnt[2] 0.367 -1.293 u_spi_master.genblk1\.data_cnt[1] SPI_MASTER_Top|I_CLK DFFC Q genblk1\.data_cnt[1] 0.367 -1.248 =================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------- u_spi_master.genblk1\.data_cnt[2] SPI_MASTER_Top|I_CLK DFFC D data_cnt_3[2] 9.867 -1.833 u_spi_master.genblk1\.rx_latch_flag SPI_MASTER_Top|I_CLK DFFC D genblk1\.rx_latch_flag5 9.867 -1.570 u_spi_master.genblk1\.data_cnt[5] SPI_MASTER_Top|I_CLK DFFC D un1_genblk1\.data_cnt_1_axbxc5 9.867 -1.441 u_spi_master.genblk1\.clock_cnt[0] SPI_MASTER_Top|I_CLK DFFC D genblk1\.clock_cnt_lm[0] 9.867 -1.349 u_spi_master.genblk1\.clock_cnt[1] SPI_MASTER_Top|I_CLK DFFC D genblk1\.clock_cnt_lm[1] 9.867 -1.349 u_spi_master.genblk1\.clock_cnt[2] SPI_MASTER_Top|I_CLK DFFC D genblk1\.clock_cnt_lm[2] 9.867 -1.349 u_spi_master.genblk1\.clock_cnt[3] SPI_MASTER_Top|I_CLK DFFC D genblk1\.clock_cnt_lm[3] 9.867 -1.349 u_spi_master.genblk1\.clock_cnt[4] SPI_MASTER_Top|I_CLK DFFC D genblk1\.clock_cnt_lm[4] 9.867 -1.349 u_spi_master.genblk1\.MOSI_MASTER SPI_MASTER_Top|I_CLK DFFCE CE un1_n_status35_2_i 9.867 -1.266 u_spi_master.genblk1\.tx_shift_data[1] SPI_MASTER_Top|I_CLK DFFCE CE un1_n_status35_2_i 9.867 -1.266 ============================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.867 - Propagation time: 11.700 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.833 Number of logic level(s): 6 Starting point: u_spi_master.genblk1\.c_status_1_rep1 / Q Ending point: u_spi_master.genblk1\.data_cnt[2] / D The start point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK The end point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- u_spi_master.genblk1\.c_status_1_rep1 DFFC Q Out 0.367 0.367 - genblk1\.c_status_1_rep1 Net - - 1.021 - 3 u_spi_master.g0_2_0_a3_1 LUT2 I1 In - 1.388 - u_spi_master.g0_2_0_a3_1 LUT2 F Out 1.099 2.487 - g0_2_0_a3_1 Net - - 0.766 - 1 u_spi_master.g0_2_0_a3 LUT4 I1 In - 3.253 - u_spi_master.g0_2_0_a3 LUT4 F Out 1.099 4.352 - genblk1\.data_cnt17_0 Net - - 1.021 - 4 u_spi_master.genblk1\.data_cnt17 LUT4 I0 In - 5.373 - u_spi_master.genblk1\.data_cnt17 LUT4 F Out 1.032 6.405 - genblk1\.data_cnt17 Net - - 0.766 - 1 u_spi_master.un1_n_status36 LUT4 I1 In - 7.170 - u_spi_master.un1_n_status36 LUT4 F Out 1.099 8.269 - un1_n_status36 Net - - 1.021 - 8 u_spi_master.un1_genblk1\.data_cnt_1_ac0_1 LUT3 I2 In - 9.290 - u_spi_master.un1_genblk1\.data_cnt_1_ac0_1 LUT3 F Out 0.822 10.112 - un1_genblk1\.data_cnt_1_c2 Net - - 0.766 - 1 u_spi_master.data_cnt_3[2] LUT3 I2 In - 10.878 - u_spi_master.data_cnt_3[2] LUT3 F Out 0.822 11.700 - data_cnt_3[2] Net - - 0.000 - 1 u_spi_master.genblk1\.data_cnt[2] DFFC D In - 11.700 - ========================================================================================================= Total path delay (propagation time + setup) of 11.833 is 6.473(54.7%) logic and 5.360(45.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.867 - Propagation time: 11.633 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.766 Number of logic level(s): 6 Starting point: u_spi_master.genblk1\.c_status_0_rep1 / Q Ending point: u_spi_master.genblk1\.data_cnt[2] / D The start point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK The end point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- u_spi_master.genblk1\.c_status_0_rep1 DFFC Q Out 0.367 0.367 - genblk1\.c_status_0_rep1 Net - - 1.021 - 3 u_spi_master.g0_2_0_a3_1 LUT2 I0 In - 1.388 - u_spi_master.g0_2_0_a3_1 LUT2 F Out 1.032 2.420 - g0_2_0_a3_1 Net - - 0.766 - 1 u_spi_master.g0_2_0_a3 LUT4 I1 In - 3.186 - u_spi_master.g0_2_0_a3 LUT4 F Out 1.099 4.285 - genblk1\.data_cnt17_0 Net - - 1.021 - 4 u_spi_master.genblk1\.data_cnt17 LUT4 I0 In - 5.306 - u_spi_master.genblk1\.data_cnt17 LUT4 F Out 1.032 6.338 - genblk1\.data_cnt17 Net - - 0.766 - 1 u_spi_master.un1_n_status36 LUT4 I1 In - 7.103 - u_spi_master.un1_n_status36 LUT4 F Out 1.099 8.202 - un1_n_status36 Net - - 1.021 - 8 u_spi_master.un1_genblk1\.data_cnt_1_ac0_1 LUT3 I2 In - 9.223 - u_spi_master.un1_genblk1\.data_cnt_1_ac0_1 LUT3 F Out 0.822 10.045 - un1_genblk1\.data_cnt_1_c2 Net - - 0.766 - 1 u_spi_master.data_cnt_3[2] LUT3 I2 In - 10.811 - u_spi_master.data_cnt_3[2] LUT3 F Out 0.822 11.633 - data_cnt_3[2] Net - - 0.000 - 1 u_spi_master.genblk1\.data_cnt[2] DFFC D In - 11.633 - ========================================================================================================= Total path delay (propagation time + setup) of 11.766 is 6.406(54.4%) logic and 5.360(45.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.867 - Propagation time: 11.437 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.570 Number of logic level(s): 6 Starting point: u_spi_master.genblk1\.clock_cnt[3] / Q Ending point: u_spi_master.genblk1\.rx_latch_flag / D The start point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK The end point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ u_spi_master.genblk1\.clock_cnt[3] DFFC Q Out 0.367 0.367 - genblk1\.clock_cnt[3] Net - - 1.021 - 8 u_spi_master.genblk1\.n_status23_x LUT3 I1 In - 1.388 - u_spi_master.genblk1\.n_status23_x LUT3 F Out 1.099 2.487 - genblk1\.n_status23_x Net - - 1.021 - 2 u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1 LUT4 I0 In - 3.508 - u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1 LUT4 F Out 1.032 4.540 - genblk1\.n_status_8_1_iv_N_3L3_1_0 Net - - 0.766 - 1 u_spi_master.genblk1\.n_status_8_1_iv_N_5L7 LUT4 I1 In - 5.306 - u_spi_master.genblk1\.n_status_8_1_iv_N_5L7 LUT4 F Out 1.099 6.405 - genblk1\.n_status_8_1_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.genblk1\.n_status_8_1_iv[0] LUT4 I2 In - 7.170 - u_spi_master.genblk1\.n_status_8_1_iv[0] LUT4 F Out 0.822 7.992 - genblk1\.n_status_8_1_iv[0] Net - - 1.021 - 18 u_spi_master.g0_0 LUT2 I0 In - 9.013 - u_spi_master.g0_0 LUT2 F Out 1.032 10.045 - genblk1\.un1_n_status_1_0 Net - - 0.766 - 1 u_spi_master.genblk1\.rx_latch_flag5 LUT4 I3 In - 10.811 - u_spi_master.genblk1\.rx_latch_flag5 LUT4 F Out 0.626 11.437 - genblk1\.rx_latch_flag5 Net - - 0.000 - 1 u_spi_master.genblk1\.rx_latch_flag DFFC D In - 11.437 - ============================================================================================================ Total path delay (propagation time + setup) of 11.570 is 6.210(53.7%) logic and 5.360(46.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.867 - Propagation time: 11.423 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.556 Number of logic level(s): 6 Starting point: u_spi_master.genblk1\.clock_cnt[2] / Q Ending point: u_spi_master.genblk1\.data_cnt[2] / D The start point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK The end point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- u_spi_master.genblk1\.clock_cnt[2] DFFC Q Out 0.367 0.367 - genblk1\.clock_cnt[2] Net - - 1.021 - 8 u_spi_master.g0_2_0_a3_sx LUT4 I1 In - 1.388 - u_spi_master.g0_2_0_a3_sx LUT4 F Out 1.099 2.487 - g0_2_0_a3_sx Net - - 0.766 - 1 u_spi_master.g0_2_0_a3 LUT4 I2 In - 3.253 - u_spi_master.g0_2_0_a3 LUT4 F Out 0.822 4.075 - genblk1\.data_cnt17_0 Net - - 1.021 - 4 u_spi_master.genblk1\.data_cnt17 LUT4 I0 In - 5.096 - u_spi_master.genblk1\.data_cnt17 LUT4 F Out 1.032 6.128 - genblk1\.data_cnt17 Net - - 0.766 - 1 u_spi_master.un1_n_status36 LUT4 I1 In - 6.893 - u_spi_master.un1_n_status36 LUT4 F Out 1.099 7.992 - un1_n_status36 Net - - 1.021 - 8 u_spi_master.un1_genblk1\.data_cnt_1_ac0_1 LUT3 I2 In - 9.013 - u_spi_master.un1_genblk1\.data_cnt_1_ac0_1 LUT3 F Out 0.822 9.835 - un1_genblk1\.data_cnt_1_c2 Net - - 0.766 - 1 u_spi_master.data_cnt_3[2] LUT3 I2 In - 10.601 - u_spi_master.data_cnt_3[2] LUT3 F Out 0.822 11.423 - data_cnt_3[2] Net - - 0.000 - 1 u_spi_master.genblk1\.data_cnt[2] DFFC D In - 11.423 - ========================================================================================================= Total path delay (propagation time + setup) of 11.556 is 6.196(53.6%) logic and 5.360(46.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.867 - Propagation time: 11.370 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.503 Number of logic level(s): 6 Starting point: u_spi_master.genblk1\.clock_cnt[2] / Q Ending point: u_spi_master.genblk1\.rx_latch_flag / D The start point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK The end point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ u_spi_master.genblk1\.clock_cnt[2] DFFC Q Out 0.367 0.367 - genblk1\.clock_cnt[2] Net - - 1.021 - 8 u_spi_master.genblk1\.n_status23_x LUT3 I0 In - 1.388 - u_spi_master.genblk1\.n_status23_x LUT3 F Out 1.032 2.420 - genblk1\.n_status23_x Net - - 1.021 - 2 u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1 LUT4 I0 In - 3.441 - u_spi_master.genblk1\.n_status_8_1_iv_N_3L3_1 LUT4 F Out 1.032 4.473 - genblk1\.n_status_8_1_iv_N_3L3_1_0 Net - - 0.766 - 1 u_spi_master.genblk1\.n_status_8_1_iv_N_5L7 LUT4 I1 In - 5.239 - u_spi_master.genblk1\.n_status_8_1_iv_N_5L7 LUT4 F Out 1.099 6.338 - genblk1\.n_status_8_1_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.genblk1\.n_status_8_1_iv[0] LUT4 I2 In - 7.103 - u_spi_master.genblk1\.n_status_8_1_iv[0] LUT4 F Out 0.822 7.925 - genblk1\.n_status_8_1_iv[0] Net - - 1.021 - 18 u_spi_master.g0_0 LUT2 I0 In - 8.946 - u_spi_master.g0_0 LUT2 F Out 1.032 9.978 - genblk1\.un1_n_status_1_0 Net - - 0.766 - 1 u_spi_master.genblk1\.rx_latch_flag5 LUT4 I3 In - 10.744 - u_spi_master.genblk1\.rx_latch_flag5 LUT4 F Out 0.626 11.370 - genblk1\.rx_latch_flag5 Net - - 0.000 - 1 u_spi_master.genblk1\.rx_latch_flag DFFC D In - 11.370 - ============================================================================================================ Total path delay (propagation time + setup) of 11.503 is 6.143(53.4%) logic and 5.360(46.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- u_spi_master.I_RESETN_i System INV O I_RESETN_i 0.000 8.846 u_spi_master.genblk1\.SCLK_MASTER_i System INV O genblk1\.SCLK_MASTER_i 0.000 8.846 =================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- u_spi_master.genblk1\.SCLK_MASTER System DFFCE D genblk1\.SCLK_MASTER_i 9.867 8.846 u_spi_master.genblk1\.SS_N_MASTER[0] System DFFP PRESET I_RESETN_i 9.867 8.846 u_spi_master.genblk1\.reg_tmt System DFFP PRESET I_RESETN_i 9.867 8.846 ========================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.867 - Propagation time: 1.021 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 8.846 Number of logic level(s): 0 Starting point: u_spi_master.I_RESETN_i / O Ending point: u_spi_master.genblk1\.SS_N_MASTER[0] / PRESET The start point is clocked by System [rising] The end point is clocked by SPI_MASTER_Top|I_CLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------- u_spi_master.I_RESETN_i INV O Out 0.000 0.000 - I_RESETN_i Net - - 1.021 - 79 u_spi_master.genblk1\.SS_N_MASTER[0] DFFP PRESET In - 1.021 - ===================================================================================================== Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB) --------------------------------------- Resource Usage Report for SPI_MASTER_Top Mapping to part: gw1n_4blqfp144-6 Cell usage: ALU 5 uses DFFC 22 uses DFFCE 54 uses DFFP 2 uses DFFPE 1 use GSR 1 use INV 2 uses MUX2_LUT5 5 uses LUT2 7 uses LUT3 39 uses LUT4 82 uses I/O Register bits: 0 Register bits not including I/Os: 79 of 3456 (2%) Total load per clock: SPI_MASTER_Top|I_CLK: 79 @S |Mapping Summary: Total LUTs: 128 (2%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 196MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Wed Sep 18 11:00:49 2019 ###########################################################]