@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\IDE\ipcore\SPIMASTER\data\spi_master_top.v":5:19:5:19|Synthesizing module SPI_MASTER_Top in library work.
@N|Running in 64-bit mode
@N: NF107 :"d:\gowin sw\v191_01beta\gowin\gowin_v1.9.1.01beta\ide\ipcore\spimaster\data\spi_master_top.v":5:19:5:19|Selected library: work cell: SPI_MASTER_Top view verilog as top level
@N: NF107 :"d:\gowin sw\v191_01beta\gowin\gowin_v1.9.1.01beta\ide\ipcore\spimaster\data\spi_master_top.v":5:19:5:19|Selected library: work cell: SPI_MASTER_Top view verilog as top level

