Project Settings
Project Name gw_spi_master Device Name rev_1: GOWIN-GW1N : GW1N_4B
Implementation Name rev_1 Top Module gw_spi_master
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 16 19 0 - 00m:01s - 2019/9/18
14:27:22
(premap)Complete 10 2 0 0m:01s 0m:01s 192MB 2019/9/18
14:27:25
(fpga_mapper)Complete 19 4 0 0m:03s 0m:03s 192MB 2019/9/18
14:27:29
Multi-srs Generator Complete2019/9/18
14:27:23

Area Summary
I/O ports (io_port) 9 Non I/O Register bits (non_io_reg) 137 (3%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 0 (10)
Block Multipliers (dsp_used) 0 (8) LUTs (total_luts) 153 (3%)

Timing Summary
Clock NameReq FreqEst FreqSlack
Gowin_PLL|clkout_inferred_clock92.6 MHz78.7 MHz-1.905
System100.0 MHz2787.1 MHz9.641

Optimizations Summary
Combined Clock Conversion 0 / 1