#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: Desktop-2019KKU # Wed Sep 18 14:27:21 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v" (library work) @I::"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v" (library work) @I::"D:\spi_master\project\gw_spi_master\src\gowin_pll\gowin_pll.v" (library work) @I::"D:\spi_master\project\gw_spi_master\src\spi_master\spi_master.v" (library work) Verilog syntax check successful! File D:\spi_master\project\gw_spi_master\src\master_sram_spi.v changed - recompiling Selecting top level module gw_spi_master @N:CG364 : gw1n.v(1488) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : gowin_pll.v(8) | Synthesizing module Gowin_PLL in library work. Running optimization stage 1 on Gowin_PLL ....... @N:CG364 : master_sram_spi.v(6) | Synthesizing module master_sram_spi in library work. Running optimization stage 1 on master_sram_spi ....... @W:CL265 : master_sram_spi.v(69) | Removing unused bit 7 of rd_status[7:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : master_sram_spi.v(69) | Pruning unused bits 3 to 0 of rd_status[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @A:CL282 : master_sram_spi.v(69) | Feedback mux created for signal rd_data[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CL190 : master_sram_spi.v(69) | Optimizing register bit I_RADDR[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : master_sram_spi.v(69) | Optimizing register bit I_RADDR[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : master_sram_spi.v(69) | Optimizing register bit I_WDATA[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : master_sram_spi.v(69) | Pruning register bit 5 of I_WDATA[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : master_sram_spi.v(69) | Pruning register bit 2 of I_RADDR[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : master_sram_spi.v(69) | Pruning register bit 0 of I_RADDR[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : gw1n.v(1552) | Synthesizing module GSR in library work. Running optimization stage 1 on GSR ....... Running optimization stage 1 on INV ....... Running optimization stage 1 on LUT4 ....... Running optimization stage 1 on LUT3 ....... Running optimization stage 1 on LUT2 ....... Running optimization stage 1 on MUX2_LUT5 ....... Running optimization stage 1 on DFFC ....... Running optimization stage 1 on DFFP ....... Running optimization stage 1 on DFFCE ....... Running optimization stage 1 on DFFPE ....... Running optimization stage 1 on ALU ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... Running optimization stage 1 on \~spi_master.SPI_MASTER_Top_ ....... @N:CG364 : spi_master.v(1998) | Synthesizing module SPI_MASTER_Top in library work. Running optimization stage 1 on SPI_MASTER_Top ....... @N:CG364 : gw_spi_master.v(6) | Synthesizing module gw_spi_master in library work. @W:CS263 : gw_spi_master.v(105) | Port-width mismatch for port wr_index. The port definition is 4 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port. @W:CG360 : gw_spi_master.v(31) | Removing wire I_RESETN, as there is no assignment to it. @W:CG360 : gw_spi_master.v(39) | Removing wire MOSI_SLAVE, as there is no assignment to it. @W:CG360 : gw_spi_master.v(41) | Removing wire SS_N_SLAVE, as there is no assignment to it. @W:CG360 : gw_spi_master.v(42) | Removing wire SCLK_SLAVE, as there is no assignment to it. Running optimization stage 1 on gw_spi_master ....... @W:CL271 : gw_spi_master.v(81) | Pruning unused bits 7 to 6 of delay_key2_5[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : gw_spi_master.v(74) | Pruning unused bits 7 to 6 of delay_rst_5[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Running optimization stage 2 on gw_spi_master ....... @W:CL156 : gw_spi_master.v(39) | *Input MOSI_SLAVE to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : gw_spi_master.v(41) | *Input SS_N_SLAVE to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : gw_spi_master.v(42) | *Input SCLK_SLAVE to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. Running optimization stage 2 on SPI_MASTER_Top ....... @N:CL159 : spi_master.v(2032) | Input MOSI_SLAVE is unused. @N:CL159 : spi_master.v(2033) | Input SS_N_SLAVE is unused. @N:CL159 : spi_master.v(2034) | Input SCLK_SLAVE is unused. Running optimization stage 2 on \~spi_master.SPI_MASTER_Top_ ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on ALU ....... Running optimization stage 2 on DFFPE ....... Running optimization stage 2 on DFFCE ....... Running optimization stage 2 on DFFP ....... Running optimization stage 2 on DFFC ....... Running optimization stage 2 on MUX2_LUT5 ....... Running optimization stage 2 on LUT2 ....... Running optimization stage 2 on LUT3 ....... Running optimization stage 2 on LUT4 ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on GSR ....... Running optimization stage 2 on master_sram_spi ....... @N:CL201 : master_sram_spi.v(69) | Trying to extract state machine for register wr_index. Extracted state machine for register wr_index State machine has 7 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 @N:CL201 : master_sram_spi.v(69) | Trying to extract state machine for register rd_reg. Extracted state machine for register rd_reg State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL279 : master_sram_spi.v(69) | Pruning register bits 4 to 3 of I_WDATA[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Running optimization stage 2 on Gowin_PLL ....... Running optimization stage 2 on PLL ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 14:27:22 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 14:27:22 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 14:27:22 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode File D:\spi_master\project\gw_spi_master\impl\synthesize\rev_1\synwork\gw_spi_master_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 18 14:27:23 2019 ###########################################################] # Wed Sep 18 14:27:23 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: gw_spi_master_scck.rpt Printing clock summary report in "D:\spi_master\project\gw_spi_master\impl\synthesize\rev_1\gw_spi_master_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design @W:FX474 : | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Encoding state machine rd_reg[3:0] (in view: work.master_sram_spi(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : master_sram_spi.v(69) | There are no possible illegal states for state machine rd_reg[3:0] (in view: work.master_sram_spi(verilog)); safe FSM implementation is not required. Encoding state machine wr_index_1[6:0] (in view: work.master_sram_spi(verilog)) original code -> new code 0000 -> 0000001 0001 -> 0000010 0010 -> 0000100 0011 -> 0001000 0100 -> 0010000 0101 -> 0100000 0110 -> 1000000 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------- 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - Gowin_PLL|clkout_inferred_clock 149.8 MHz 6.675 inferred Autoconstr_clkgroup_0 144 ====================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------------------------------------------- System 0 - - - - Gowin_PLL|clkout_inferred_clock 144 u_pll1.pll_inst.CLKOUT(PLL) clk_en_0.C - - ============================================================================================================================= @W:MT529 : master_sram_spi.v(69) | Found inferred clock Gowin_PLL|clkout_inferred_clock which controls 144 sequential elements including u_master_sram_spi.wr_index_1[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 144 clock pin(s) of sequential element(s) 0 instances converted, 144 sequential instances remain driven by gated/generated clocks ======================================================= Gated/Generated Clocks ======================================================= Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------- ClockId_0_1 u_pll1.pll_inst.CLKOUT PLL 144 counter0[0] Black box on clock path ====================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\spi_master\project\gw_spi_master\impl\synthesize\rev_1\gw_spi_master.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 106MB peak: 192MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Sep 18 14:27:25 2019 ###########################################################] # Wed Sep 18 14:27:25 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled @N:FX493 : | Applying initial value "0" on instance u_master_sram_spi.err_flag_reg. @N:FX493 : | Applying initial value "0" on instance u_master_sram_spi.r_flag_reg. @N:FX493 : | Applying initial value "000000000000000" on instance counter0[14:0]. @N:FX493 : | Applying initial value "000000" on instance delay_key2[5:0]. @N:FX493 : | Applying initial value "000000" on instance delay_rst[5:0]. @N:FX493 : | Applying initial value "0" on instance clk_en. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) @W:BN132 : master_sram_spi.v(69) | Removing instance u_master_sram_spi.I_WDATA_1[7] because it is equivalent to instance u_master_sram_spi.I_WDATA_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : master_sram_spi.v(69) | Removing instance u_master_sram_spi.I_WDATA_1[6] because it is equivalent to instance u_master_sram_spi.I_WDATA_1[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 191MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 191MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 191MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 191MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -4.63ns 174 / 63 2 0h:00m:00s -4.63ns 174 / 63 @N:FX271 : gw_spi_master.v(74) | Replicating instance delay_rst[4] (in view: work.gw_spi_master(verilog)) with 4 loads 1 time to improve timing. Timing driven replication report Added 1 Registers via timing driven replication Added 0 LUTs via timing driven replication 3 0h:00m:01s -4.38ns 178 / 64 @N:FX271 : gw_spi_master.v(74) | Replicating instance delay_rst[3] (in view: work.gw_spi_master(verilog)) with 4 loads 1 time to improve timing. Timing driven replication report Added 1 Registers via timing driven replication Added 0 LUTs via timing driven replication 4 0h:00m:01s -4.38ns 174 / 65 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 119MB peak: 191MB) Writing Analyst data base D:\spi_master\project\gw_spi_master\impl\synthesize\rev_1\synwork\gw_spi_master_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 192MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 192MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 189MB peak: 192MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 190MB peak: 192MB) Warning: Found 3 combinational loops! 1) instance \\genblk1\.n_status_8_1_iv_cZ\[2\] (in view: work.\\\~spi_master\.SPI_MASTER_Top_\ (verilog)), output net \\genblk1\.n_status_8_1_iv_cZ\[2\] (in view: work.\\\~spi_master\.SPI_MASTER_Top_\ (verilog)) net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[2\] input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_4L5/I0 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_4L5 (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_4L5/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_1[2] input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[2\]/I1 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[2\] (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[2\]/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[2\] 2) instance \\genblk1\.n_status_8_1_iv_cZ\[0\] (in view: work.\\\~spi_master\.SPI_MASTER_Top_\ (verilog)), output net \\genblk1\.n_status_8_1_iv_cZ\[0\] (in view: work.\\\~spi_master\.SPI_MASTER_Top_\ (verilog)) net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[0\] input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_3L3_1/I1 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_3L3_1 (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_3L3_1/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_3L3_1_0 input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_5L7_cZ/I1 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_5L7_cZ (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_5L7_cZ/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_N_5L7 input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[0\]/I2 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[0\] (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[0\]/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_1_iv_cZ\[0\] 3) instance \\genblk1\.n_status_8_0_iv_cZ\[1\] (in view: work.\\\~spi_master\.SPI_MASTER_Top_\ (verilog)), output net \\genblk1\.n_status_8_0_iv_cZ\[1\] (in view: work.\\\~spi_master\.SPI_MASTER_Top_\ (verilog)) net u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_3L3/I1 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_3L3 (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_3L3/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_1[1] input pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\]/I1 instance u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] (cell LUT4) output pin u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\]/F net u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] End of loops @W:MT246 : gowin_pll.v(21) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Gowin_PLL|clkout_inferred_clock with period 10.80ns. Please declare a user-defined clock on net u_pll1.clkout_25m. ##### START OF TIMING REPORT #####[ # Timing report written on Wed Sep 18 14:27:29 2019 # Top view: gw_spi_master Requested Frequency: 92.6 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.905 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------ Gowin_PLL|clkout_inferred_clock 92.6 MHz 78.7 MHz 10.795 12.700 -1.905 inferred Autoconstr_clkgroup_0 System 100.0 MHz 2787.1 MHz 10.000 0.359 9.641 system system_clkgroup ========================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------- System Gowin_PLL|clkout_inferred_clock | 10.795 9.641 | No paths - | No paths - | No paths - Gowin_PLL|clkout_inferred_clock System | 10.795 6.960 | No paths - | No paths - | No paths - Gowin_PLL|clkout_inferred_clock Gowin_PLL|clkout_inferred_clock | 10.795 -1.905 | No paths - | No paths - | No paths - ========================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Gowin_PLL|clkout_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- delay_rst[5] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst[5] 0.367 -1.905 delay_rst[2] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst[2] 0.367 -1.838 delay_rst_fast[3] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst_fast[3] 0.367 -1.628 delay_rst_fast[4] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst_fast[4] 0.367 -1.432 delay_rst[1] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst[1] 0.367 -1.128 u_spi_master.u_spi_master.\\genblk1\.c_status_1_rep1_Z Gowin_PLL|clkout_inferred_clock DFFC Q \\genblk1\.c_status_1_rep1 0.367 -1.038 delay_rst[0] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst[0] 0.367 -0.981 u_spi_master.u_spi_master.\\genblk1\.c_status_0_rep1_Z Gowin_PLL|clkout_inferred_clock DFFC Q \\genblk1\.c_status_0_rep1 0.367 -0.971 u_spi_master.u_spi_master.\\genblk1\.clock_cnt_Z\[3\] Gowin_PLL|clkout_inferred_clock DFFC Q \\genblk1\.clock_cnt[3] 0.367 -0.775 u_spi_master.u_spi_master.\\genblk1\.clock_cnt_Z\[2\] Gowin_PLL|clkout_inferred_clock DFFC Q \\genblk1\.clock_cnt[2] 0.367 -0.761 ================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[1\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[2\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[3\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[4\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[5\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[6\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[7\] Gowin_PLL|clkout_inferred_clock DFFCE CE g0_0_0 10.662 -1.905 u_spi_master.u_spi_master.\\genblk1\.data_cnt_Z\[2\] Gowin_PLL|clkout_inferred_clock DFFC D data_cnt_3[2] 10.662 -1.038 u_spi_master.u_spi_master.\\genblk1\.rx_latch_flag_Z Gowin_PLL|clkout_inferred_clock DFFC D \\genblk1\.rx_latch_flag5 10.662 -0.775 ===================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.795 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.662 - Propagation time: 12.567 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.905 Number of logic level(s): 8 Starting point: delay_rst[5] / Q Ending point: u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER / CE The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- delay_rst[5] DFFE Q Out 0.367 0.367 - delay_rst[5] Net - - 1.021 - 5 G_8_0_0 LUT4 I1 In - 1.388 - G_8_0_0 LUT4 F Out 1.099 2.487 - G_8_0_0 Net - - 0.000 - 1 G_8_0 MUX2_LUT5 I0 In - 2.487 - G_8_0 MUX2_LUT5 O Out 0.150 2.637 - G_8_0 Net - - 0.000 - 1 G_8 MUX2_LUT6 I0 In - 2.637 - G_8 MUX2_LUT6 O Out 0.177 2.814 - rstn1_i Net - - 1.021 - 6 u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 I0 In - 3.835 - u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 F Out 1.032 4.867 - n_status_3_sqmuxa_s5_1_d_0 Net - - 1.021 - 2 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 I3 In - 5.888 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 F Out 0.626 6.514 - \\genblk1\.n_status_8_0_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 I3 In - 7.280 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 F Out 0.626 7.906 - \\genblk1\.n_status_8_0_iv_cZ\[1\] Net - - 1.021 - 18 u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 I0 In - 8.927 - u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 F Out 1.032 9.959 - g0_0_a3_1 Net - - 0.766 - 1 u_spi_master.u_spi_master.g0_0_0 LUT4 I2 In - 10.724 - u_spi_master.u_spi_master.g0_0_0 LUT4 F Out 0.822 11.546 - g0_0_0 Net - - 1.021 - 8 u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER DFFCE CE In - 12.567 - ================================================================================================================================= Total path delay (propagation time + setup) of 12.700 is 6.064(47.7%) logic and 6.636(52.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.795 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.662 - Propagation time: 12.567 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.905 Number of logic level(s): 8 Starting point: delay_rst[5] / Q Ending point: u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER / CE The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- delay_rst[5] DFFE Q Out 0.367 0.367 - delay_rst[5] Net - - 1.021 - 5 G_8_0_1 LUT4 I1 In - 1.388 - G_8_0_1 LUT4 F Out 1.099 2.487 - G_8_0_1 Net - - 0.000 - 1 G_8_0 MUX2_LUT5 I1 In - 2.487 - G_8_0 MUX2_LUT5 O Out 0.150 2.637 - G_8_0 Net - - 0.000 - 1 G_8 MUX2_LUT6 I0 In - 2.637 - G_8 MUX2_LUT6 O Out 0.177 2.814 - rstn1_i Net - - 1.021 - 6 u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 I0 In - 3.835 - u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 F Out 1.032 4.867 - n_status_3_sqmuxa_s5_1_d_0 Net - - 1.021 - 2 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 I3 In - 5.888 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 F Out 0.626 6.514 - \\genblk1\.n_status_8_0_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 I3 In - 7.280 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 F Out 0.626 7.906 - \\genblk1\.n_status_8_0_iv_cZ\[1\] Net - - 1.021 - 18 u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 I0 In - 8.927 - u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 F Out 1.032 9.959 - g0_0_a3_1 Net - - 0.766 - 1 u_spi_master.u_spi_master.g0_0_0 LUT4 I2 In - 10.724 - u_spi_master.u_spi_master.g0_0_0 LUT4 F Out 0.822 11.546 - g0_0_0 Net - - 1.021 - 8 u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER DFFCE CE In - 12.567 - ================================================================================================================================= Total path delay (propagation time + setup) of 12.700 is 6.064(47.7%) logic and 6.636(52.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.795 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.662 - Propagation time: 12.567 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.905 Number of logic level(s): 8 Starting point: delay_rst[5] / Q Ending point: u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER / CE The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- delay_rst[5] DFFE Q Out 0.367 0.367 - delay_rst[5] Net - - 1.021 - 5 G_8_1_1 LUT4 I1 In - 1.388 - G_8_1_1 LUT4 F Out 1.099 2.487 - G_8_1_1 Net - - 0.000 - 1 G_8_1 MUX2_LUT5 I1 In - 2.487 - G_8_1 MUX2_LUT5 O Out 0.150 2.637 - G_8_1 Net - - 0.000 - 1 G_8 MUX2_LUT6 I1 In - 2.637 - G_8 MUX2_LUT6 O Out 0.177 2.814 - rstn1_i Net - - 1.021 - 6 u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 I0 In - 3.835 - u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 F Out 1.032 4.867 - n_status_3_sqmuxa_s5_1_d_0 Net - - 1.021 - 2 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 I3 In - 5.888 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 F Out 0.626 6.514 - \\genblk1\.n_status_8_0_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 I3 In - 7.280 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 F Out 0.626 7.906 - \\genblk1\.n_status_8_0_iv_cZ\[1\] Net - - 1.021 - 18 u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 I0 In - 8.927 - u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 F Out 1.032 9.959 - g0_0_a3_1 Net - - 0.766 - 1 u_spi_master.u_spi_master.g0_0_0 LUT4 I2 In - 10.724 - u_spi_master.u_spi_master.g0_0_0 LUT4 F Out 0.822 11.546 - g0_0_0 Net - - 1.021 - 8 u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER DFFCE CE In - 12.567 - ================================================================================================================================= Total path delay (propagation time + setup) of 12.700 is 6.064(47.7%) logic and 6.636(52.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.795 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.662 - Propagation time: 12.567 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.905 Number of logic level(s): 8 Starting point: delay_rst[5] / Q Ending point: u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER / CE The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- delay_rst[5] DFFE Q Out 0.367 0.367 - delay_rst[5] Net - - 1.021 - 5 G_8_1_0 LUT4 I1 In - 1.388 - G_8_1_0 LUT4 F Out 1.099 2.487 - G_8_1_0 Net - - 0.000 - 1 G_8_1 MUX2_LUT5 I0 In - 2.487 - G_8_1 MUX2_LUT5 O Out 0.150 2.637 - G_8_1 Net - - 0.000 - 1 G_8 MUX2_LUT6 I1 In - 2.637 - G_8 MUX2_LUT6 O Out 0.177 2.814 - rstn1_i Net - - 1.021 - 6 u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 I0 In - 3.835 - u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 F Out 1.032 4.867 - n_status_3_sqmuxa_s5_1_d_0 Net - - 1.021 - 2 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 I3 In - 5.888 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 F Out 0.626 6.514 - \\genblk1\.n_status_8_0_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 I3 In - 7.280 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 F Out 0.626 7.906 - \\genblk1\.n_status_8_0_iv_cZ\[1\] Net - - 1.021 - 18 u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 I0 In - 8.927 - u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 F Out 1.032 9.959 - g0_0_a3_1 Net - - 0.766 - 1 u_spi_master.u_spi_master.g0_0_0 LUT4 I2 In - 10.724 - u_spi_master.u_spi_master.g0_0_0 LUT4 F Out 0.822 11.546 - g0_0_0 Net - - 1.021 - 8 u_spi_master.u_spi_master.\\genblk1\.MOSI_MASTER DFFCE CE In - 12.567 - ================================================================================================================================= Total path delay (propagation time + setup) of 12.700 is 6.064(47.7%) logic and 6.636(52.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.795 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.662 - Propagation time: 12.567 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.905 Number of logic level(s): 8 Starting point: delay_rst[5] / Q Ending point: u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[7\] / CE The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- delay_rst[5] DFFE Q Out 0.367 0.367 - delay_rst[5] Net - - 1.021 - 5 G_8_0_0 LUT4 I1 In - 1.388 - G_8_0_0 LUT4 F Out 1.099 2.487 - G_8_0_0 Net - - 0.000 - 1 G_8_0 MUX2_LUT5 I0 In - 2.487 - G_8_0 MUX2_LUT5 O Out 0.150 2.637 - G_8_0 Net - - 0.000 - 1 G_8 MUX2_LUT6 I0 In - 2.637 - G_8 MUX2_LUT6 O Out 0.177 2.814 - rstn1_i Net - - 1.021 - 6 u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 I0 In - 3.835 - u_spi_master.u_spi_master.n_status_3_sqmuxa_s5_1_d_0_cZ LUT4 F Out 1.032 4.867 - n_status_3_sqmuxa_s5_1_d_0 Net - - 1.021 - 2 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 I3 In - 5.888 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_N_5L7_cZ LUT4 F Out 0.626 6.514 - \\genblk1\.n_status_8_0_iv_N_5L7 Net - - 0.766 - 1 u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 I3 In - 7.280 - u_spi_master.u_spi_master.\\genblk1\.n_status_8_0_iv_cZ\[1\] LUT4 F Out 0.626 7.906 - \\genblk1\.n_status_8_0_iv_cZ\[1\] Net - - 1.021 - 18 u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 I0 In - 8.927 - u_spi_master.u_spi_master.g0_0_a3_1_cZ LUT4 F Out 1.032 9.959 - g0_0_a3_1 Net - - 0.766 - 1 u_spi_master.u_spi_master.g0_0_0 LUT4 I2 In - 10.724 - u_spi_master.u_spi_master.g0_0_0 LUT4 F Out 0.822 11.546 - g0_0_0 Net - - 1.021 - 8 u_spi_master.u_spi_master.\\genblk1\.tx_shift_data_Z\[7\] DFFCE CE In - 12.567 - ================================================================================================================================= Total path delay (propagation time + setup) of 12.700 is 6.064(47.7%) logic and 6.636(52.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------- u_spi_master.u_spi_master.\\genblk1\.SCLK_MASTER_i_cZ System INV O \\genblk1\.SCLK_MASTER_i 0.000 9.641 u_spi_master.u_spi_master.I_RESETN_i_cZ System INV O I_RESETN_i 0.000 9.641 u_master_sram_spi.wr_index_1_i[6] System INV O wr_index_1_i[6] 0.000 9.641 u_master_sram_spi.wr_reg_i[0] System INV O wr_reg_i[0] 0.000 9.641 ======================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------- u_spi_master.u_spi_master.\\genblk1\.SCLK_MASTER System DFFCE D \\genblk1\.SCLK_MASTER_i 10.662 9.641 u_spi_master.u_spi_master.\\genblk1\.SS_N_MASTER\[0\] System DFFP PRESET I_RESETN_i 10.662 9.641 u_spi_master.u_spi_master.\\genblk1\.reg_tmt_Z System DFFP PRESET I_RESETN_i 10.662 9.641 u_master_sram_spi.I_WDATA_1[0] System DFFCE D wr_index_1_i[6] 10.662 9.641 u_master_sram_spi.wr_reg[0] System DFFCE D wr_reg_i[0] 10.662 9.641 ============================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.795 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.662 - Propagation time: 1.021 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.641 Number of logic level(s): 0 Starting point: u_spi_master.u_spi_master.\\genblk1\.SCLK_MASTER_i_cZ / O Ending point: u_spi_master.u_spi_master.\\genblk1\.SCLK_MASTER / D The start point is clocked by System [rising] The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------- u_spi_master.u_spi_master.\\genblk1\.SCLK_MASTER_i_cZ INV O Out 0.000 0.000 - \\genblk1\.SCLK_MASTER_i Net - - 1.021 - 1 u_spi_master.u_spi_master.\\genblk1\.SCLK_MASTER DFFCE D In - 1.021 - ===================================================================================================================== Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 192MB) --------------------------------------- Resource Usage Report for gw_spi_master Mapping to part: gw1n_4blqfp144-6 Cell usage: ALU 20 uses DFF 10 uses DFFC 29 uses DFFCE 66 uses DFFE 22 uses DFFP 3 uses DFFPE 1 use DFFR 6 uses GSR 1 use INV 4 uses MUX2_LUT5 7 uses MUX2_LUT6 1 use PLL 1 use LUT2 17 uses LUT3 46 uses LUT4 90 uses I/O ports: 9 I/O primitives: 9 IBUF 4 uses OBUF 5 uses I/O Register bits: 0 Register bits not including I/Os: 137 of 3456 (3%) Total load per clock: Gowin_PLL|clkout_inferred_clock: 137 @S |Mapping Summary: Total LUTs: 153 (3%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 40MB peak: 192MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Wed Sep 18 14:27:29 2019 ###########################################################]