@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT529 :"d:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Found inferred clock Gowin_PLL|clkout_inferred_clock which controls 144 sequential elements including u_master_sram_spi.wr_index_1[6]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
