@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MO225 :"d:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|There are no possible illegal states for state machine rd_reg[3:0] (in view: work.master_sram_spi(verilog)); safe FSM implementation is not required.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file D:\spi_master\project\gw_spi_master\impl\synthesize\rev_1\gw_spi_master.sap.
