@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "0" on instance u_master_sram_spi.err_flag_reg.
@N: FX493 |Applying initial value "0" on instance u_master_sram_spi.r_flag_reg.
@N: FX493 |Applying initial value "000000000000000" on instance counter0[14:0].
@N: FX493 |Applying initial value "000000" on instance delay_key2[5:0].
@N: FX493 |Applying initial value "000000" on instance delay_rst[5:0].
@N: FX493 |Applying initial value "0" on instance clk_en.
@N: FX271 :"d:\spi_master\project\gw_spi_master\src\gw_spi_master.v":74:1:74:6|Replicating instance delay_rst[4] (in view: work.gw_spi_master(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"d:\spi_master\project\gw_spi_master\src\gw_spi_master.v":74:1:74:6|Replicating instance delay_rst[3] (in view: work.gw_spi_master(verilog)) with 4 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
