@W: CL265 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Removing unused bit 7 of rd_status[7:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Pruning unused bits 3 to 0 of rd_status[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Optimizing register bit I_RADDR[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Optimizing register bit I_RADDR[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Optimizing register bit I_WDATA[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Pruning register bit 5 of I_WDATA[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Pruning register bit 2 of I_RADDR[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Pruning register bit 0 of I_RADDR[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CS263 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":105:23:105:30|Port-width mismatch for port wr_index. The port definition is 4 bits, but the actual port connection bit width is 1. Adjust either the definition or the instantiation of this port.
@W: CG360 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":31:27:31:34|Removing wire I_RESETN, as there is no assignment to it.
@W: CG360 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":39:27:39:36|Removing wire MOSI_SLAVE, as there is no assignment to it.
@W: CG360 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":41:27:41:36|Removing wire SS_N_SLAVE, as there is no assignment to it.
@W: CG360 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":42:27:42:36|Removing wire SCLK_SLAVE, as there is no assignment to it.
@W: CL271 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":81:1:81:6|Pruning unused bits 7 to 6 of delay_key2_5[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":74:1:74:6|Pruning unused bits 7 to 6 of delay_rst_5[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL156 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":39:27:39:36|*Input MOSI_SLAVE to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":41:27:41:36|*Input SS_N_SLAVE to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"D:\spi_master\project\gw_spi_master\src\gw_spi_master.v":42:27:42:36|*Input SCLK_SLAVE to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL279 :"D:\spi_master\project\gw_spi_master\src\master_sram_spi.v":69:0:69:5|Pruning register bits 4 to 3 of I_WDATA[4:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

