Timing Messages

Report Title	Gowin Timing Analysis Report
Design File	D:\spi_master\project\gw_spi_master\impl\synthesize\rev_1\gw_spi_master.vm
Physical Constraints File	D:\spi_master\project\gw_spi_master\src\gw_spi_master.cst
Timing Constraint File	D:\spi_master\project\gw_spi_master\src\gw_spi_master.sdc
GOWIN version	V1.9.1.01Beta
Part Number	GW1N-LV4LQ144C6/I5
Created Time	Wed Sep 18 14:27:34 2019
Legal Announcement	Copyright (C)2014-2019 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C
Hold Delay Model	Fast 1.26V 0C
Numbers of Paths Analyzed	333
Numbers of Endpoints Analyzed	336
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk_50m	Base	20.000	50.000	0.000	10.000			clk_50m
clk_25m	Generated	40.000	25.000	0.000	20.000	clk_50m	clk_50m	clkout_25m
u_pll1/pll_inst/CLKOUTP.default_gen_clk	Generated	40.000	25.000	0.000	20.000		clk_50m
u_pll1/pll_inst/CLKOUTD.default_gen_clk	Generated	80.000	12.500	0.000	40.000		clk_50m
u_pll1/pll_inst/CLKOUTD3.default_gen_clk	Generated	120.000	8.333	0.000	60.000		clk_50m

Max Frequency Summary:

NO.	Clock Name	Fmax	Entity
1	clk_25m	60.939(MHz)	TOP

No timing paths to get frequency of clk_50m!

No timing paths to get frequency of u_pll1/pll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_pll1/pll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_pll1/pll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_50m	Setup	0.000	0
clk_50m	Hold	0.000	0
clk_25m	Setup	0.000	0
clk_25m	Hold	0.000	0
u_pll1/pll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_pll1/pll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_pll1/pll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
u_pll1/pll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
u_pll1/pll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_pll1/pll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	26.172	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.MOSI_MASTER/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	13.585
2	26.198	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	13.202
3	26.369	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.reg_trdy_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	13.388
4	26.588	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	13.169
5	26.940	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.816
6	26.940	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.816
7	26.940	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[6]_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.816
8	26.940	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[7]_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.816
9	26.940	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.816
10	26.940	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[5]_Z/CE	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.816
11	27.027	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.373
12	27.088	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.reg_trdy_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	12.312
13	27.676	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	11.724
14	28.068	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	11.332
15	28.074	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	11.326
16	28.074	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	11.326
17	28.130	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_fast_Z[0]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	11.270
18	28.465	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	10.935
19	28.933	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	10.467
20	29.533	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	9.867
21	29.682	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	9.718
22	30.668	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	8.732
23	31.276	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	8.124
24	31.399	delay_key2_Z[0]/Q	u_master_sram_spi/I_TX_EN/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	8.001
25	31.408	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/D	clk_25m:[R]	clk_25m:[R]	40.000	0.000	7.992

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.571	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.571
2	0.571	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.571
3	0.571	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.571
4	0.571	delay_key2_Z[3]/Q	delay_key2_Z[4]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.571
5	0.576	delay_key2_Z[2]/Q	delay_key2_Z[3]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.576
6	0.709	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.709
7	0.709	u_master_sram_spi/I_RX_EN/Q	u_master_sram_spi/I_RX_EN/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.709
8	0.710	u_master_sram_spi/wr_index_1_Z[6]/Q	u_master_sram_spi/wr_index_1_Z[6]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.710
9	0.710	u_master_sram_spi/wr_index_1_Z[1]/Q	u_master_sram_spi/wr_index_1_Z[1]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.710
10	0.710	u_master_sram_spi/wr_reg_Z[0]/Q	u_master_sram_spi/wr_reg_Z[0]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.710
11	0.710	u_master_sram_spi/wr_index_1_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[2]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.710
12	0.711	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.711
13	0.711	u_master_sram_spi/rd_reg_Z[1]/Q	u_master_sram_spi/rd_reg_Z[1]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.711
14	0.712	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.712
15	0.712	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.712
16	0.712	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/Q	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.712
17	0.714	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.714
18	0.835	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/Q	u_spi_master/u_spi_master/reg_rxdata_Z[3]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.835
19	0.835	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z/Q	u_spi_master/u_spi_master/reg_rxdata_Z[2]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.835
20	0.835	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z/Q	u_spi_master/u_spi_master/reg_rxdata_Z[1]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.835
21	0.839	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/Q	u_spi_master/u_spi_master/reg_rxdata_Z[3]/CE	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.854
22	0.839	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/Q	u_spi_master/u_spi_master/reg_rxdata_Z[0]/CE	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.854
23	0.853	counter0_Z[1]/Q	counter0_Z[1]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.853
24	0.853	counter0_Z[11]/Q	counter0_Z[11]/D	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.853
25	0.874	u_master_sram_spi/wr_index_1_Z[0]/Q	u_master_sram_spi/wr_cntl_Z[0]/CE	clk_25m:[R]	clk_25m:[R]	0.000	0.000	0.889

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
2	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
3	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
4	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
5	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
6	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
7	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_Z[1]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
8	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/reg_txdata_Z[0]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
9	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
10	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
11	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
12	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
13	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_Z[2]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
14	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/reg_txdata_Z[1]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
15	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
16	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
17	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
18	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
19	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
20	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.data_cnt_Z[3]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
21	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
22	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
23	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
24	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867
25	32.890	delay_rst_Z[1]/Q	u_spi_master/u_spi_master/reg_txdata_Z[2]/CLEAR	clk_25m:[R]	clk_25m:[R]	40.000	0.000	6.867

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.746	delay_rst_Z[2]/Q	u_master_sram_spi/I_WDATA_1[0]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.761
2	1.746	delay_rst_Z[2]/Q	u_master_sram_spi/I_WADDR_Z[2]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.761
3	1.746	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[1]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.761
4	1.746	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[0]/PRESET	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.761
5	1.746	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[6]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.761
6	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/rd_reg_Z[0]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
7	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/I_RX_EN/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
8	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/rd_status_Z[4]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
9	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/rd_reg_Z[1]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
10	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/rd_status_Z[5]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
11	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[3]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
12	1.789	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[2]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.804
13	1.805	delay_rst_Z[2]/Q	u_master_sram_spi/receive_flag_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.820
14	1.808	delay_rst_Z[2]/Q	u_master_sram_spi/I_WADDR_Z[0]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.823
15	1.808	delay_rst_Z[2]/Q	u_master_sram_spi/I_TX_EN/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.823
16	1.811	delay_rst_Z[2]/Q	u_master_sram_spi/wr_cntl_Z[0]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.826
17	1.811	delay_rst_Z[2]/Q	u_master_sram_spi/start_dl_Z/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.826
18	1.811	delay_rst_Z[2]/Q	u_master_sram_spi/I_WADDR_Z[1]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	1.826
19	2.004	delay_rst_Z[2]/Q	u_master_sram_spi/I_WDATA_1[1]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.019
20	2.004	delay_rst_Z[2]/Q	u_master_sram_spi/I_WDATA_1[2]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.019
21	2.094	delay_rst_Z[2]/Q	u_master_sram_spi/wr_reg_Z[0]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.109
22	2.094	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[4]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.109
23	2.094	delay_rst_Z[2]/Q	u_master_sram_spi/I_RADDR_1[1]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.109
24	2.094	delay_rst_Z[2]/Q	u_master_sram_spi/wr_index_1_Z[5]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.109
25	2.352	delay_rst_Z[2]/Q	u_master_sram_spi/rd_status_Z[6]/CLEAR	clk_25m:[R]	clk_25m:[R]	0.000	0.000	2.367

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	17.864	19.114	1.250	Low Pulse Width	clk_25m	delay_rst_fast_Z[3]
2	17.864	19.114	1.250	Low Pulse Width	clk_25m	clk_en_0
3	17.864	19.114	1.250	Low Pulse Width	clk_25m	counter0_Z[2]
4	17.864	19.114	1.250	Low Pulse Width	clk_25m	delay_rst_Z[3]
5	17.864	19.114	1.250	Low Pulse Width	clk_25m	u_master_sram_spi/start_dl_Z
6	17.864	19.114	1.250	Low Pulse Width	clk_25m	u_master_sram_spi/err_flag_reg_0
7	17.864	19.114	1.250	Low Pulse Width	clk_25m	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]
8	17.864	19.114	1.250	Low Pulse Width	clk_25m	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z
9	17.864	19.114	1.250	Low Pulse Width	clk_25m	u_master_sram_spi/r_flag_reg_0
10	17.864	19.114	1.250	Low Pulse Width	clk_25m	u_spi_master/u_spi_master/genblk1.SS_N_MASTER[0]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	26.172
Data Arrival Time	16.710
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.MOSI_MASTER
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
16.710	1.502	tNET	RR	1	IOT12[A]	u_spi_master/u_spi_master/genblk1.MOSI_MASTER/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	IOT12[A]	u_spi_master/u_spi_master/genblk1.MOSI_MASTER/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.MOSI_MASTER
42.883	-0.043	tSu		1	IOT12[A]	u_spi_master/u_spi_master/genblk1.MOSI_MASTER

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 30.616%; route: 8.967, 66.010%; tC2Q: 0.458, 3.374%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	26.198
Data Arrival Time	16.328
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.402	1.184	tNET	FF	1	R9C12[3][A]	u_spi_master/u_spi_master/g0_0/I0
15.501	1.099	tINS	FF	1	R9C12[3][A]	u_spi_master/u_spi_master/g0_0/F
15.506	0.005	tNET	FF	1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag5_cZ/I3
16.328	0.822	tINS	FF	1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag5_cZ/F
16.328	0.000	tNET	FF	1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z
42.526	-0.400	tSu		1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 5.278, 39.978%; route: 7.466, 56.551%; tC2Q: 0.458, 3.472%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	26.369
Data Arrival Time	16.513
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.reg_trdy_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.737	1.519	tNET	FF	1	R9C13[3][A]	u_spi_master/u_spi_master/genblk1.un1_reg_txdata_0_sqmuxa_1_cZ/I1
15.798	1.061	tINS	FR	1	R9C13[3][A]	u_spi_master/u_spi_master/genblk1.un1_reg_txdata_0_sqmuxa_1_cZ/F
16.513	0.715	tNET	RR	1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.reg_trdy_Z
42.883	-0.043	tSu		1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.418, 33.001%; route: 8.511, 63.576%; tC2Q: 0.458, 3.424%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	26.588
Data Arrival Time	16.295
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
16.295	1.087	tNET	RR	1	R8C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z
42.883	-0.043	tSu		1	R8C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 31.581%; route: 8.552, 64.938%; tC2Q: 0.458, 3.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	26.940
Data Arrival Time	15.942
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
15.942	0.734	tNET	RR	1	R9C14[1][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[1][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]
42.883	-0.043	tSu		1	R9C14[1][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 32.451%; route: 8.199, 63.973%; tC2Q: 0.458, 3.576%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	26.940
Data Arrival Time	15.942
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
15.942	0.734	tNET	RR	1	R9C14[2][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[2][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z
42.883	-0.043	tSu		1	R9C14[2][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 32.451%; route: 8.199, 63.973%; tC2Q: 0.458, 3.576%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	26.940
Data Arrival Time	15.942
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[6]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
15.942	0.734	tNET	RR	1	R9C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[6]_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[6]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[6]_Z
42.883	-0.043	tSu		1	R9C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[6]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 32.451%; route: 8.199, 63.973%; tC2Q: 0.458, 3.576%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	26.940
Data Arrival Time	15.942
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[7]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
15.942	0.734	tNET	RR	1	R9C14[2][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[7]_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[2][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[7]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[7]_Z
42.883	-0.043	tSu		1	R9C14[2][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[7]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 32.451%; route: 8.199, 63.973%; tC2Q: 0.458, 3.576%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	26.940
Data Arrival Time	15.942
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
15.942	0.734	tNET	RR	1	R9C14[1][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[1][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z
42.883	-0.043	tSu		1	R9C14[1][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 32.451%; route: 8.199, 63.973%; tC2Q: 0.458, 3.576%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	26.940
Data Arrival Time	15.942
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[5]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/I1
15.208	0.802	tINS	FR	8	R9C14[3][A]	u_spi_master/u_spi_master/g0_0_0_cZ/F
15.942	0.734	tNET	RR	1	R9C14[0][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[5]_Z/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[0][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[5]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[5]_Z
42.883	-0.043	tSu		1	R9C14[0][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[5]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.159, 32.451%; route: 8.199, 63.973%; tC2Q: 0.458, 3.576%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	27.027
Data Arrival Time	15.499
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.236	1.018	tNET	FF	1	R9C12[2][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[4]/I0
15.335	1.099	tINS	FF	1	R9C12[2][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[4]/F
15.335	0.000	tNET	FF	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[4]/I1
15.484	0.149	tINS	FF	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[4]/O
15.499	0.015	tNET	FF	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
42.526	-0.400	tSu		1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.605, 37.219%; route: 7.310, 59.077%; tC2Q: 0.458, 3.704%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	27.088
Data Arrival Time	15.438
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.reg_trdy_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.406	1.188	tNET	FF	1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy9_cZ/I0
15.438	1.032	tINS	FF	1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy9_cZ/F
15.438	0.000	tNET	FF	1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.reg_trdy_Z
42.526	-0.400	tSu		1	R9C13[1][A]	u_spi_master/u_spi_master/genblk1.reg_trdy_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.389, 35.647%; route: 7.465, 60.631%; tC2Q: 0.458, 3.723%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	27.676
Data Arrival Time	14.850
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.217	0.625	tINS	FR	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
13.653	0.436	tNET	RR	1	R13C13[2][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[3]/I0
14.685	1.032	tINS	RF	1	R13C13[2][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[3]/F
14.685	0.000	tNET	FF	1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[3]/I1
14.834	0.149	tINS	FF	1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[3]/O
14.850	0.015	tNET	FF	1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z
42.526	-0.400	tSu		1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.537, 38.699%; route: 6.728, 57.391%; tC2Q: 0.458, 3.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	28.068
Data Arrival Time	14.458
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
13.262	0.044	tNET	FF	1	R13C12[2][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[0]/I0
14.294	1.032	tINS	FF	1	R13C12[2][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[0]/F
14.294	0.000	tNET	FF	1	R13C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[0]/I1
14.443	0.149	tINS	FF	1	R13C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[0]/O
14.458	0.015	tNET	FF	1	R13C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z
42.526	-0.400	tSu		1	R13C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.538, 40.045%; route: 6.336, 55.910%; tC2Q: 0.458, 4.045%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	28.074
Data Arrival Time	14.452
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.217	0.625	tINS	FR	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
13.661	0.444	tNET	RR	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_0_cZ[2]/I0
14.287	0.626	tINS	RF	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_0_cZ[2]/F
14.287	0.000	tNET	FF	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[2]/I0
14.436	0.149	tINS	FF	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[2]/O
14.452	0.015	tNET	FF	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z
42.526	-0.400	tSu		1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.131, 36.475%; route: 6.736, 59.478%; tC2Q: 0.458, 4.047%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	28.074
Data Arrival Time	14.452
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.217	0.625	tINS	FR	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
13.661	0.444	tNET	RR	1	R13C13[0][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[1]/I0
14.287	0.626	tINS	RF	1	R13C13[0][B]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0_1_cZ[1]/F
14.287	0.000	tNET	FF	1	R13C13[0][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[1]/I1
14.436	0.149	tINS	FF	1	R13C13[0][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_lm_0[1]/O
14.452	0.015	tNET	FF	1	R13C13[0][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C13[0][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]
42.526	-0.400	tSu		1	R13C13[0][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.131, 36.475%; route: 6.736, 59.478%; tC2Q: 0.458, 4.047%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	28.130
Data Arrival Time	14.396
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_fast_Z[0]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.396	1.178	tNET	FF	1	R12C14[0][B]	u_spi_master/u_spi_master/genblk1.c_status_fast_Z[0]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R12C14[0][B]	u_spi_master/u_spi_master/genblk1.c_status_fast_Z[0]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_fast_Z[0]_Z
42.526	-0.400	tSu		1	R12C14[0][B]	u_spi_master/u_spi_master/genblk1.c_status_fast_Z[0]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 3.357, 29.786%; route: 7.455, 66.147%; tC2Q: 0.458, 4.067%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	28.465
Data Arrival Time	14.061
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
14.061	0.843	tNET	FF	1	R12C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R12C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z
42.526	-0.400	tSu		1	R12C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 3.357, 30.700%; route: 7.120, 65.109%; tC2Q: 0.458, 4.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack	28.933
Data Arrival Time	13.593
Data Required Time	42.526
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
10.445	4.151	tNET	FF	1	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/I0
11.477	1.032	tINS	FF	2	R13C12[0][B]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_0_cZ/F
11.488	0.011	tNET	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/I3
12.587	1.099	tINS	FF	1	R13C12[1][A]	u_spi_master/u_spi_master/n_status_3_sqmuxa_s5_1_d_cZ/F
12.592	0.005	tNET	FF	1	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/I3
13.218	0.626	tINS	FF	18	R13C12[3][B]	u_spi_master/u_spi_master/genblk1.n_status_8_1_iv_cZ[0]_cZ/F
13.593	0.375	tNET	FF	1	R13C12[0][A]	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C12[0][A]	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z
42.526	-0.400	tSu		1	R13C12[0][A]	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 3.357, 32.073%; route: 6.652, 63.549%; tC2Q: 0.458, 4.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack	29.533
Data Arrival Time	12.993
Data Required Time	42.526
From	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
3.584	0.458	tC2Q	RF	8	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q
5.387	1.802	tNET	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/I3
6.013	0.626	tINS	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/F
6.018	0.005	tNET	FF	1	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/I2
7.117	1.099	tINS	FF	4	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/F
7.932	0.815	tNET	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/I1
8.558	0.626	tINS	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/F
8.564	0.005	tNET	FF	1	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/I3
9.596	1.032	tINS	FF	8	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/F
10.917	1.322	tNET	FF	1	R9C12[3][B]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_ac0_1/I2
11.542	0.625	tINS	FR	1	R9C12[3][B]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_ac0_1/F
11.961	0.419	tNET	RR	1	R9C11[1][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[2]/I2
12.993	1.032	tINS	RF	1	R9C11[1][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[2]/F
12.993	0.000	tNET	FF	1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z
42.526	-0.400	tSu		1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 5.040, 51.077%; route: 4.369, 44.278%; tC2Q: 0.458, 4.645%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	29.682
Data Arrival Time	12.844
Data Required Time	42.526
From	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
3.584	0.458	tC2Q	RF	8	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q
5.387	1.802	tNET	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/I3
6.013	0.626	tINS	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/F
6.018	0.005	tNET	FF	1	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/I2
7.117	1.099	tINS	FF	4	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/F
7.932	0.815	tNET	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/I1
8.558	0.626	tINS	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/F
8.564	0.005	tNET	FF	1	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/I3
9.596	1.032	tINS	FF	8	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/F
10.917	1.322	tNET	FF	1	R9C12[0][B]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_ac0_3/I3
11.739	0.822	tINS	FF	1	R9C12[0][B]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_ac0_3/F
11.745	0.005	tNET	FF	1	R9C12[1][A]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_axbxc5_cZ/I3
12.844	1.099	tINS	FF	1	R9C12[1][A]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_axbxc5_cZ/F
12.844	0.000	tNET	FF	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
42.526	-0.400	tSu		1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 5.304, 54.579%; route: 3.956, 40.705%; tC2Q: 0.458, 4.716%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack	30.668
Data Arrival Time	11.858
Data Required Time	42.526
From	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
3.584	0.458	tC2Q	RF	8	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q
5.387	1.802	tNET	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/I3
6.013	0.626	tINS	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/F
6.018	0.005	tNET	FF	1	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/I2
7.117	1.099	tINS	FF	4	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/F
7.932	0.815	tNET	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/I1
8.558	0.626	tINS	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/F
8.564	0.005	tNET	FF	1	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/I3
9.596	1.032	tINS	FF	8	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/F
10.759	1.163	tNET	FF	1	R11C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[1]/I3
11.858	1.099	tINS	FF	1	R11C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[1]/F
11.858	0.000	tNET	FF	1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z
42.526	-0.400	tSu		1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.482, 51.327%; route: 3.792, 43.424%; tC2Q: 0.458, 5.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	31.276
Data Arrival Time	11.250
Data Required Time	42.526
From	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
3.584	0.458	tC2Q	RF	8	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q
5.387	1.802	tNET	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/I3
6.013	0.626	tINS	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/F
6.018	0.005	tNET	FF	1	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/I2
7.117	1.099	tINS	FF	4	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/F
7.932	0.815	tNET	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/I1
8.558	0.626	tINS	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/F
8.564	0.005	tNET	FF	1	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/I3
9.596	1.032	tINS	FF	8	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/F
10.428	0.832	tNET	FF	1	R11C12[0][B]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_axbxc4_cZ/I3
11.250	0.822	tINS	FF	1	R11C12[0][B]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_axbxc4_cZ/F
11.250	0.000	tNET	FF	1	R11C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R11C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z
42.526	-0.400	tSu		1	R11C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.205, 51.757%; route: 3.461, 42.601%; tC2Q: 0.458, 5.641%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	31.399
Data Arrival Time	11.127
Data Required Time	42.526
From	delay_key2_Z[0]
To	u_master_sram_spi/I_TX_EN
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	IOB10[A]	delay_key2_Z[0]/CLK
3.584	0.458	tC2Q	RF	2	IOB10[A]	delay_key2_Z[0]/Q
5.064	1.480	tNET	FF	1	R12C8[0][B]	start_3_cZ/I0
6.163	1.099	tINS	FF	1	R12C8[0][B]	start_3_cZ/F
6.168	0.005	tNET	FF	1	R12C8[0][A]	start_cZ/I2
7.267	1.099	tINS	FF	2	R12C8[0][A]	start_cZ/F
8.076	0.809	tNET	FF	1	R13C9[0][B]	u_master_sram_spi/I_WADDR_0_sqmuxa_0_a3_0_a3/I0
9.175	1.099	tINS	FF	2	R13C9[0][B]	u_master_sram_spi/I_WADDR_0_sqmuxa_0_a3_0_a3/F
9.186	0.011	tNET	FF	1	R13C9[0][A]	u_master_sram_spi/un1_I_TX_EN_0_sqmuxa_0_0_0_cZ/I1
10.285	1.099	tINS	FF	7	R13C9[0][A]	u_master_sram_spi/un1_I_TX_EN_0_sqmuxa_0_0_0_cZ/F
11.127	0.842	tNET	FF	1	R11C9[0][A]	u_master_sram_spi/I_TX_EN/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R11C9[0][A]	u_master_sram_spi/I_TX_EN/CLK
42.926	-0.200	tUnc				u_master_sram_spi/I_TX_EN
42.526	-0.400	tSu		1	R11C9[0][A]	u_master_sram_spi/I_TX_EN

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.396, 54.941%; route: 3.147, 39.331%; tC2Q: 0.458, 5.728%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	31.408
Data Arrival Time	11.118
Data Required Time	42.526
From	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
3.584	0.458	tC2Q	RF	8	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/Q
5.387	1.802	tNET	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/I3
6.013	0.626	tINS	FF	1	R13C14[1][B]	u_spi_master/u_spi_master/g0_2_0_a3_sx_cZ/F
6.018	0.005	tNET	FF	1	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/I2
7.117	1.099	tINS	FF	4	R13C14[3][A]	u_spi_master/u_spi_master/g0_2_0_a3/F
7.932	0.815	tNET	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/I1
8.558	0.626	tINS	FF	1	R12C13[3][B]	u_spi_master/u_spi_master/genblk1.un1_n_status36_1_cZ/F
8.564	0.005	tNET	FF	1	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/I3
9.590	1.026	tINS	FR	8	R12C13[0][A]	u_spi_master/u_spi_master/un1_n_status36_cZ_cZ/F
10.019	0.429	tNET	RR	1	R12C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_fast_cZ[1]/I3
11.118	1.099	tINS	RF	1	R12C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_fast_cZ[1]/F
11.118	0.000	tNET	FF	1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z
42.526	-0.400	tSu		1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 4.476, 56.008%; route: 3.057, 38.257%; tC2Q: 0.458, 5.735%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.571
Data Arrival Time	3.061
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C11[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z/CLK
2.824	0.333	tC2Q	RR	2	R9C11[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z/Q
3.061	0.238	tNET	RR	1	R9C11[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C11[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]
2.491	0.000	tHld		1	R9C11[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	0.571
Data Arrival Time	3.061
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/CLK
2.824	0.333	tC2Q	RR	2	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/Q
3.061	0.238	tNET	RR	1	R8C12[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z
2.491	0.000	tHld		1	R8C12[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	0.571
Data Arrival Time	3.061
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/CLK
2.824	0.333	tC2Q	RR	2	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/Q
3.061	0.238	tNET	RR	1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z
2.491	0.000	tHld		1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	0.571
Data Arrival Time	3.061
Data Required Time	2.491
From	delay_key2_Z[3]
To	delay_key2_Z[4]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C8[0][A]	delay_key2_Z[3]/CLK
2.824	0.333	tC2Q	RR	2	R12C8[0][A]	delay_key2_Z[3]/Q
3.061	0.238	tNET	RR	1	R12C8[0][B]	delay_key2_Z[4]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C8[0][B]	delay_key2_Z[4]/CLK
2.491	0.000	tUnc				delay_key2_Z[4]
2.491	0.000	tHld		1	R12C8[0][B]	delay_key2_Z[4]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	0.576
Data Arrival Time	3.067
Data Required Time	2.491
From	delay_key2_Z[2]
To	delay_key2_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C8[1][B]	delay_key2_Z[2]/CLK
2.824	0.333	tC2Q	RR	2	R12C8[1][B]	delay_key2_Z[2]/Q
3.067	0.243	tNET	RR	1	R12C8[0][A]	delay_key2_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C8[0][A]	delay_key2_Z[3]/CLK
2.491	0.000	tUnc				delay_key2_Z[3]
2.491	0.000	tHld		1	R12C8[0][A]	delay_key2_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.243, 42.123%; tC2Q: 0.333, 57.877%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	0.709
Data Arrival Time	3.199
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/CLK
2.824	0.333	tC2Q	RR	4	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/Q
2.827	0.004	tNET	RR	1	R12C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_fast_cZ[1]/I1
3.199	0.372	tINS	RF	1	R12C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_fast_cZ[1]/F
3.199	0.000	tNET	FF	1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z
2.491	0.000	tHld		1	R12C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_fast_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	0.709
Data Arrival Time	3.199
Data Required Time	2.491
From	u_master_sram_spi/I_RX_EN
To	u_master_sram_spi/I_RX_EN
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C9[1][A]	u_master_sram_spi/I_RX_EN/CLK
2.824	0.333	tC2Q	RR	10	R9C9[1][A]	u_master_sram_spi/I_RX_EN/Q
2.827	0.004	tNET	RR	1	R9C9[1][A]	u_master_sram_spi/N_47_i_cZ/I0
3.199	0.372	tINS	RF	1	R9C9[1][A]	u_master_sram_spi/N_47_i_cZ/F
3.199	0.000	tNET	FF	1	R9C9[1][A]	u_master_sram_spi/I_RX_EN/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C9[1][A]	u_master_sram_spi/I_RX_EN/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_RX_EN
2.491	0.000	tHld		1	R9C9[1][A]	u_master_sram_spi/I_RX_EN

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	0.710
Data Arrival Time	3.201
Data Required Time	2.491
From	u_master_sram_spi/wr_index_1_Z[6]
To	u_master_sram_spi/wr_index_1_Z[6]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]/CLK
2.824	0.333	tC2Q	RR	6	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]/Q
2.829	0.005	tNET	RR	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_ns_6_0_.m26_i/I1
3.201	0.372	tINS	RF	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_ns_6_0_.m26_i/F
3.201	0.000	tNET	FF	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[6]
2.491	0.000	tHld		1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	0.710
Data Arrival Time	3.201
Data Required Time	2.491
From	u_master_sram_spi/wr_index_1_Z[1]
To	u_master_sram_spi/wr_index_1_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]/CLK
2.824	0.333	tC2Q	RR	6	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]/Q
2.829	0.005	tNET	RR	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_ns_6_0_.m6_i/I2
3.201	0.372	tINS	RF	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_ns_6_0_.m6_i/F
3.201	0.000	tNET	FF	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[1]
2.491	0.000	tHld		1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	0.710
Data Arrival Time	3.201
Data Required Time	2.491
From	u_master_sram_spi/wr_reg_Z[0]
To	u_master_sram_spi/wr_reg_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]/CLK
2.824	0.333	tC2Q	RR	8	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]/Q
2.829	0.005	tNET	RR	1	R8C9[1][A]	u_master_sram_spi/wr_reg_i_cZ[0]/I0
3.201	0.372	tINS	RF	1	R8C9[1][A]	u_master_sram_spi/wr_reg_i_cZ[0]/F
3.201	0.000	tNET	FF	1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_reg_Z[0]
2.491	0.000	tHld		1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	0.710
Data Arrival Time	3.201
Data Required Time	2.491
From	u_master_sram_spi/wr_index_1_Z[2]
To	u_master_sram_spi/wr_index_1_Z[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]/CLK
2.824	0.333	tC2Q	RR	7	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]/Q
2.829	0.005	tNET	RR	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_ns_6_0_.m13_i/I2
3.201	0.372	tINS	RF	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_ns_6_0_.m13_i/F
3.201	0.000	tNET	FF	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[2]
2.491	0.000	tHld		1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	0.711
Data Arrival Time	3.202
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/CLK
2.824	0.333	tC2Q	RR	10	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/Q
2.830	0.006	tNET	RR	1	R9C12[1][A]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_axbxc5_cZ/I2
3.202	0.372	tINS	RF	1	R9C12[1][A]	u_spi_master/u_spi_master/un1_genblk1.data_cnt_1_axbxc5_cZ/F
3.202	0.000	tNET	FF	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
2.491	0.000	tHld		1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	0.711
Data Arrival Time	3.202
Data Required Time	2.491
From	u_master_sram_spi/rd_reg_Z[1]
To	u_master_sram_spi/rd_reg_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]/CLK
2.824	0.333	tC2Q	RR	7	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]/Q
2.830	0.006	tNET	RR	1	R9C10[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.N_50_i/I2
3.202	0.372	tINS	RF	1	R9C10[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.N_50_i/F
3.202	0.000	tNET	FF	1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/rd_reg_Z[1]
2.491	0.000	tHld		1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	0.712
Data Arrival Time	3.203
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/CLK
2.824	0.333	tC2Q	RR	8	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/Q
2.831	0.007	tNET	RR	1	R9C11[1][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[2]/I0
3.203	0.372	tINS	RF	1	R9C11[1][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[2]/F
3.203	0.000	tNET	FF	1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z
2.491	0.000	tHld		1	R9C11[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	0.712
Data Arrival Time	3.203
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z/CLK
2.824	0.333	tC2Q	RR	11	R12C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z/Q
2.831	0.007	tNET	RR	1	R12C12[1][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[0]/I0
3.203	0.372	tINS	RF	1	R12C12[1][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[0]/F
3.203	0.000	tNET	FF	1	R12C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z
2.491	0.000	tHld		1	R12C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[0]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	0.712
Data Arrival Time	3.203
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.SCLK_MASTER
To	u_spi_master/u_spi_master/genblk1.SCLK_MASTER
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/CLK
2.824	0.333	tC2Q	RR	7	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/Q
2.831	0.007	tNET	RR	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER_i_cZ/I0
3.203	0.372	tINS	RF	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER_i_cZ/F
3.203	0.000	tNET	FF	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.SCLK_MASTER
2.491	0.000	tHld		1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	0.714
Data Arrival Time	3.204
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/CLK
2.824	0.333	tC2Q	RR	9	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/Q
2.832	0.008	tNET	RR	1	R11C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[1]/I1
3.204	0.372	tINS	RF	1	R11C12[0][A]	u_spi_master/u_spi_master/data_cnt_3_cZ[1]/F
3.204	0.000	tNET	FF	1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z
2.491	0.000	tHld		1	R11C12[0][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	0.835
Data Arrival Time	3.325
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z
To	u_spi_master/u_spi_master/reg_rxdata_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/CLK
2.824	0.333	tC2Q	RR	2	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/Q
3.325	0.501	tNET	RR	1	R9C12[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[3]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[3]/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/reg_rxdata_Z[3]
2.491	0.000	tHld		1	R9C12[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack	0.835
Data Arrival Time	3.325
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z
To	u_spi_master/u_spi_master/reg_rxdata_Z[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z/CLK
2.824	0.333	tC2Q	RR	2	R8C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z/Q
3.325	0.501	tNET	RR	1	R8C13[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[2]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C13[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[2]/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/reg_rxdata_Z[2]
2.491	0.000	tHld		1	R8C13[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack	0.835
Data Arrival Time	3.325
Data Required Time	2.491
From	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z
To	u_spi_master/u_spi_master/reg_rxdata_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C12[2][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z/CLK
2.824	0.333	tC2Q	RR	2	R8C12[2][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z/Q
3.325	0.501	tNET	RR	1	R8C13[0][B]	u_spi_master/u_spi_master/reg_rxdata_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C13[0][B]	u_spi_master/u_spi_master/reg_rxdata_Z[1]/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/reg_rxdata_Z[1]
2.491	0.000	tHld		1	R8C13[0][B]	u_spi_master/u_spi_master/reg_rxdata_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	0.839
Data Arrival Time	3.345
Data Required Time	2.506
From	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z
To	u_spi_master/u_spi_master/reg_rxdata_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/CLK
2.824	0.333	tC2Q	RR	8	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/Q
3.345	0.521	tNET	RR	1	R9C12[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[3]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[3]/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/reg_rxdata_Z[3]
2.506	0.015	tHld		1	R9C12[0][A]	u_spi_master/u_spi_master/reg_rxdata_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 60.980%; tC2Q: 0.333, 39.020%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack	0.839
Data Arrival Time	3.345
Data Required Time	2.506
From	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z
To	u_spi_master/u_spi_master/reg_rxdata_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/CLK
2.824	0.333	tC2Q	RR	8	R9C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_latch_flag_Z/Q
3.345	0.521	tNET	RR	1	R9C12[0][B]	u_spi_master/u_spi_master/reg_rxdata_Z[0]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C12[0][B]	u_spi_master/u_spi_master/reg_rxdata_Z[0]/CLK
2.491	0.000	tUnc				u_spi_master/u_spi_master/reg_rxdata_Z[0]
2.506	0.015	tHld		1	R9C12[0][B]	u_spi_master/u_spi_master/reg_rxdata_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.521, 60.980%; tC2Q: 0.333, 39.020%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	0.853
Data Arrival Time	3.343
Data Required Time	2.491
From	counter0_Z[1]
To	counter0_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C6[1][B]	counter0_Z[1]/CLK
2.824	0.333	tC2Q	RR	2	R8C6[1][B]	counter0_Z[1]/Q
2.826	0.002	tNET	RR	2	R8C6[1][B]	un2_counter0_cry_1_0/I0
3.343	0.517	tINS	RF	1	R8C6[1][B]	un2_counter0_cry_1_0/SUM
3.343	0.000	tNET	FF	1	R8C6[1][B]	counter0_Z[1]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C6[1][B]	counter0_Z[1]/CLK
2.491	0.000	tUnc				counter0_Z[1]
2.491	0.000	tHld		1	R8C6[1][B]	counter0_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	0.853
Data Arrival Time	3.343
Data Required Time	2.491
From	counter0_Z[11]
To	counter0_Z[11]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C8[0][B]	counter0_Z[11]/CLK
2.824	0.333	tC2Q	RR	2	R8C8[0][B]	counter0_Z[11]/Q
2.826	0.002	tNET	RR	2	R8C8[0][B]	un2_counter0_cry_11_0/I0
3.343	0.517	tINS	RF	1	R8C8[0][B]	un2_counter0_cry_11_0/SUM
3.343	0.000	tNET	FF	1	R8C8[0][B]	counter0_Z[11]/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C8[0][B]	counter0_Z[11]/CLK
2.491	0.000	tUnc				counter0_Z[11]
2.491	0.000	tHld		1	R8C8[0][B]	counter0_Z[11]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	0.874
Data Arrival Time	3.380
Data Required Time	2.506
From	u_master_sram_spi/wr_index_1_Z[0]
To	u_master_sram_spi/wr_cntl_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[0][B]	u_master_sram_spi/wr_index_1_Z[0]/CLK
2.824	0.333	tC2Q	RR	5	R13C10[0][B]	u_master_sram_spi/wr_index_1_Z[0]/Q
3.380	0.556	tNET	RR	1	R13C9[0][A]	u_master_sram_spi/wr_cntl_Z[0]/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C9[0][A]	u_master_sram_spi/wr_cntl_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_cntl_Z[0]
2.506	0.015	tHld		1	R13C9[0][A]	u_master_sram_spi/wr_cntl_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	0
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.556, 62.510%; tC2Q: 0.333, 37.490%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z
42.883	-0.043	tSu		1	R13C13[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[3]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z
42.883	-0.043	tSu		1	R8C12[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C12[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C12[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z
42.883	-0.043	tSu		1	R8C12[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[5]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R11C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R11C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z
42.883	-0.043	tSu		1	R11C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C11[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C11[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z
42.883	-0.043	tSu		1	R9C11[0][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[6]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z
42.883	-0.043	tSu		1	R9C12[1][A]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[5]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R12C13[2][B]	u_spi_master/u_spi_master/genblk1.c_status_Z[1]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R12C13[2][B]	u_spi_master/u_spi_master/genblk1.c_status_Z[1]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_Z[1]_Z
42.883	-0.043	tSu		1	R12C13[2][B]	u_spi_master/u_spi_master/genblk1.c_status_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/reg_txdata_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C14[2][B]	u_spi_master/u_spi_master/reg_txdata_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C14[2][B]	u_spi_master/u_spi_master/reg_txdata_Z[0]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/reg_txdata_Z[0]
42.883	-0.043	tSu		1	R8C14[2][B]	u_spi_master/u_spi_master/reg_txdata_Z[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C12[2][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C12[2][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z
42.883	-0.043	tSu		1	R8C12[2][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.SCLK_MASTER
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.SCLK_MASTER
42.883	-0.043	tSu		1	R13C14[0][A]	u_spi_master/u_spi_master/genblk1.SCLK_MASTER

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C11[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C11[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]
42.883	-0.043	tSu		1	R9C11[0][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[7]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z
42.883	-0.043	tSu		1	R8C14[0][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[1]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_Z[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R11C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R11C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[2]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_Z[2]
42.883	-0.043	tSu		1	R11C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/reg_txdata_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C14[1][B]	u_spi_master/u_spi_master/reg_txdata_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C14[1][B]	u_spi_master/u_spi_master/reg_txdata_Z[1]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/reg_txdata_Z[1]
42.883	-0.043	tSu		1	R8C14[1][B]	u_spi_master/u_spi_master/reg_txdata_Z[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z
42.883	-0.043	tSu		1	R9C12[2][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C14[2][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[2][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z
42.883	-0.043	tSu		1	R9C14[2][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z
42.883	-0.043	tSu		1	R8C12[1][B]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z
42.883	-0.043	tSu		1	R13C13[1][A]	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[2]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C14[1][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[1][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]
42.883	-0.043	tSu		1	R9C14[1][B]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.data_cnt_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R12C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R12C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[3]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.data_cnt_Z[3]
42.883	-0.043	tSu		1	R12C12[0][B]	u_spi_master/u_spi_master/genblk1.data_cnt_Z[3]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R13C12[0][A]	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R13C12[0][A]	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z
42.883	-0.043	tSu		1	R13C12[0][A]	u_spi_master/u_spi_master/genblk1.c_status_0_rep1_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R9C14[1][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R9C14[1][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z
42.883	-0.043	tSu		1	R9C14[1][A]	u_spi_master/u_spi_master/genblk1.tx_shift_data_Z[4]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z
42.883	-0.043	tSu		1	R8C12[1][A]	u_spi_master/u_spi_master/genblk1.rx_shift_data_Z[3]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[2][A]	G_8_1_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[2][A]	G_8_1_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I1
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R12C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R12C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z
42.883	-0.043	tSu		1	R12C13[2][A]	u_spi_master/u_spi_master/genblk1.c_status_Z[0]_Z

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	32.890
Data Arrival Time	9.993
Data Required Time	42.883
From	delay_rst_Z[1]
To	u_spi_master/u_spi_master/reg_txdata_Z[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
3.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
3.126	0.000	tNET	RR	1	R13C8[0][A]	delay_rst_Z[1]/CLK
3.584	0.458	tC2Q	RF	4	R13C8[0][A]	delay_rst_Z[1]/Q
5.694	2.110	tNET	FF	1	R13C8[3][A]	G_8_0_cZ/S0
6.131	0.437	tINS	FF	1	R13C8[3][A]	G_8_0_cZ/O
6.131	0.000	tNET	FF	1	R13C8[2][B]	G_8/I0
6.294	0.163	tINS	FF	77	R13C8[2][B]	G_8/O
9.993	3.699	tNET	FF	1	R11C14[1][B]	u_spi_master/u_spi_master/reg_txdata_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					clk_25m(shadow)
43.126	3.126	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
43.126	0.000	tNET	RR	1	R11C14[1][B]	u_spi_master/u_spi_master/reg_txdata_Z[2]/CLK
42.926	-0.200	tUnc				u_spi_master/u_spi_master/reg_txdata_Z[2]
42.883	-0.043	tSu		1	R11C14[1][B]	u_spi_master/u_spi_master/reg_txdata_Z[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.600, 8.738%; route: 5.808, 84.588%; tC2Q: 0.458, 6.675%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.746
Data Arrival Time	4.252
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_WDATA_1[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.252	0.805	tNET	RR	1	R13C10[2][A]	u_master_sram_spi/I_WDATA_1[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[2][A]	u_master_sram_spi/I_WDATA_1[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_WDATA_1[0]
2.506	0.015	tHld		1	R13C10[2][A]	u_master_sram_spi/I_WDATA_1[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.861%; route: 1.043, 59.212%; tC2Q: 0.333, 18.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack	1.746
Data Arrival Time	4.252
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_WADDR_Z[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.252	0.805	tNET	RR	1	R13C10[2][B]	u_master_sram_spi/I_WADDR_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[2][B]	u_master_sram_spi/I_WADDR_Z[2]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_WADDR_Z[2]
2.506	0.015	tHld		1	R13C10[2][B]	u_master_sram_spi/I_WADDR_Z[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.861%; route: 1.043, 59.212%; tC2Q: 0.333, 18.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path3

Path Summary:

Slack	1.746
Data Arrival Time	4.252
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.252	0.805	tNET	RR	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[1]
2.506	0.015	tHld		1	R13C10[1][A]	u_master_sram_spi/wr_index_1_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.861%; route: 1.043, 59.212%; tC2Q: 0.333, 18.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path4

Path Summary:

Slack	1.746
Data Arrival Time	4.252
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.252	0.805	tNET	RR	1	R13C10[0][B]	u_master_sram_spi/wr_index_1_Z[0]/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[0][B]	u_master_sram_spi/wr_index_1_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[0]
2.506	0.015	tHld		1	R13C10[0][B]	u_master_sram_spi/wr_index_1_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.861%; route: 1.043, 59.212%; tC2Q: 0.333, 18.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path5

Path Summary:

Slack	1.746
Data Arrival Time	4.252
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[6]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.252	0.805	tNET	RR	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[6]
2.506	0.015	tHld		1	R13C10[0][A]	u_master_sram_spi/wr_index_1_Z[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.861%; route: 1.043, 59.212%; tC2Q: 0.333, 18.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path6

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/rd_reg_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C10[1][B]	u_master_sram_spi/rd_reg_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[1][B]	u_master_sram_spi/rd_reg_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/rd_reg_Z[0]
2.506	0.015	tHld		1	R9C10[1][B]	u_master_sram_spi/rd_reg_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path7

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_RX_EN
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C9[1][A]	u_master_sram_spi/I_RX_EN/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C9[1][A]	u_master_sram_spi/I_RX_EN/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_RX_EN
2.506	0.015	tHld		1	R9C9[1][A]	u_master_sram_spi/I_RX_EN

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path8

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/rd_status_Z[4]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C10[2][B]	u_master_sram_spi/rd_status_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[2][B]	u_master_sram_spi/rd_status_Z[4]/CLK
2.491	0.000	tUnc				u_master_sram_spi/rd_status_Z[4]
2.506	0.015	tHld		1	R9C10[2][B]	u_master_sram_spi/rd_status_Z[4]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path9

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/rd_reg_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/rd_reg_Z[1]
2.506	0.015	tHld		1	R9C10[1][A]	u_master_sram_spi/rd_reg_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/rd_status_Z[5]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C10[2][A]	u_master_sram_spi/rd_status_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[2][A]	u_master_sram_spi/rd_status_Z[5]/CLK
2.491	0.000	tUnc				u_master_sram_spi/rd_status_Z[5]
2.506	0.015	tHld		1	R9C10[2][A]	u_master_sram_spi/rd_status_Z[5]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path11

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[3]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C9[2][A]	u_master_sram_spi/wr_index_1_Z[3]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C9[2][A]	u_master_sram_spi/wr_index_1_Z[3]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[3]
2.506	0.015	tHld		1	R9C9[2][A]	u_master_sram_spi/wr_index_1_Z[3]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path12

Path Summary:

Slack	1.789
Data Arrival Time	4.294
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.294	0.848	tNET	RR	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[2]
2.506	0.015	tHld		1	R9C10[0][A]	u_master_sram_spi/wr_index_1_Z[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.344%; route: 1.085, 60.177%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path13

Path Summary:

Slack	1.805
Data Arrival Time	4.311
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/receive_flag_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.311	0.864	tNET	RR	1	R12C10[0][A]	u_master_sram_spi/receive_flag_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R12C10[0][A]	u_master_sram_spi/receive_flag_Z/CLK
2.491	0.000	tUnc				u_master_sram_spi/receive_flag_Z
2.506	0.015	tHld		1	R12C10[0][A]	u_master_sram_spi/receive_flag_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.149%; route: 1.102, 60.540%; tC2Q: 0.333, 18.311%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path14

Path Summary:

Slack	1.808
Data Arrival Time	4.313
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_WADDR_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.313	0.867	tNET	RR	1	R11C9[1][A]	u_master_sram_spi/I_WADDR_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R11C9[1][A]	u_master_sram_spi/I_WADDR_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_WADDR_Z[0]
2.506	0.015	tHld		1	R11C9[1][A]	u_master_sram_spi/I_WADDR_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.123%; route: 1.104, 60.589%; tC2Q: 0.333, 18.288%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path15

Path Summary:

Slack	1.808
Data Arrival Time	4.313
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_TX_EN
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.313	0.867	tNET	RR	1	R11C9[0][A]	u_master_sram_spi/I_TX_EN/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R11C9[0][A]	u_master_sram_spi/I_TX_EN/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_TX_EN
2.506	0.015	tHld		1	R11C9[0][A]	u_master_sram_spi/I_TX_EN

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.123%; route: 1.104, 60.589%; tC2Q: 0.333, 18.288%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path16

Path Summary:

Slack	1.811
Data Arrival Time	4.317
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_cntl_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.317	0.870	tNET	RR	1	R13C9[0][A]	u_master_sram_spi/wr_cntl_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C9[0][A]	u_master_sram_spi/wr_cntl_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_cntl_Z[0]
2.506	0.015	tHld		1	R13C9[0][A]	u_master_sram_spi/wr_cntl_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.079%; route: 1.108, 60.670%; tC2Q: 0.333, 18.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	1.811
Data Arrival Time	4.317
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/start_dl_Z
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.317	0.870	tNET	RR	1	R13C9[2][A]	u_master_sram_spi/start_dl_Z/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C9[2][A]	u_master_sram_spi/start_dl_Z/CLK
2.491	0.000	tUnc				u_master_sram_spi/start_dl_Z
2.506	0.015	tHld		1	R13C9[2][A]	u_master_sram_spi/start_dl_Z

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.079%; route: 1.108, 60.670%; tC2Q: 0.333, 18.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path18

Path Summary:

Slack	1.811
Data Arrival Time	4.317
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_WADDR_Z[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.317	0.870	tNET	RR	1	R13C9[1][A]	u_master_sram_spi/I_WADDR_Z[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C9[1][A]	u_master_sram_spi/I_WADDR_Z[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_WADDR_Z[1]
2.506	0.015	tHld		1	R13C9[1][A]	u_master_sram_spi/I_WADDR_Z[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 21.079%; route: 1.108, 60.670%; tC2Q: 0.333, 18.250%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path19

Path Summary:

Slack	2.004
Data Arrival Time	4.509
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_WDATA_1[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.509	1.063	tNET	RR	1	R11C10[1][A]	u_master_sram_spi/I_WDATA_1[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R11C10[1][A]	u_master_sram_spi/I_WDATA_1[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_WDATA_1[1]
2.506	0.015	tHld		1	R11C10[1][A]	u_master_sram_spi/I_WDATA_1[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 19.072%; route: 1.300, 64.415%; tC2Q: 0.333, 16.513%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path20

Path Summary:

Slack	2.004
Data Arrival Time	4.509
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_WDATA_1[2]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.509	1.063	tNET	RR	1	R11C10[0][A]	u_master_sram_spi/I_WDATA_1[2]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R11C10[0][A]	u_master_sram_spi/I_WDATA_1[2]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_WDATA_1[2]
2.506	0.015	tHld		1	R11C10[0][A]	u_master_sram_spi/I_WDATA_1[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 19.072%; route: 1.300, 64.415%; tC2Q: 0.333, 16.513%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path21

Path Summary:

Slack	2.094
Data Arrival Time	4.600
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_reg_Z[0]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.600	1.153	tNET	RR	1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_reg_Z[0]
2.506	0.015	tHld		1	R8C9[1][A]	u_master_sram_spi/wr_reg_Z[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 18.253%; route: 1.391, 65.944%; tC2Q: 0.333, 15.803%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path22

Path Summary:

Slack	2.094
Data Arrival Time	4.600
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[4]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.600	1.153	tNET	RR	1	R8C9[2][A]	u_master_sram_spi/wr_index_1_Z[4]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C9[2][A]	u_master_sram_spi/wr_index_1_Z[4]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[4]
2.506	0.015	tHld		1	R8C9[2][A]	u_master_sram_spi/wr_index_1_Z[4]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 18.253%; route: 1.391, 65.944%; tC2Q: 0.333, 15.803%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path23

Path Summary:

Slack	2.094
Data Arrival Time	4.600
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/I_RADDR_1[1]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.600	1.153	tNET	RR	1	R8C9[0][A]	u_master_sram_spi/I_RADDR_1[1]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C9[0][A]	u_master_sram_spi/I_RADDR_1[1]/CLK
2.491	0.000	tUnc				u_master_sram_spi/I_RADDR_1[1]
2.506	0.015	tHld		1	R8C9[0][A]	u_master_sram_spi/I_RADDR_1[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 18.253%; route: 1.391, 65.944%; tC2Q: 0.333, 15.803%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path24

Path Summary:

Slack	2.094
Data Arrival Time	4.600
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/wr_index_1_Z[5]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.600	1.153	tNET	RR	1	R8C9[2][B]	u_master_sram_spi/wr_index_1_Z[5]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C9[2][B]	u_master_sram_spi/wr_index_1_Z[5]/CLK
2.491	0.000	tUnc				u_master_sram_spi/wr_index_1_Z[5]
2.506	0.015	tHld		1	R8C9[2][B]	u_master_sram_spi/wr_index_1_Z[5]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 18.253%; route: 1.391, 65.944%; tC2Q: 0.333, 15.803%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path25

Path Summary:

Slack	2.352
Data Arrival Time	4.858
Data Required Time	2.506
From	delay_rst_Z[2]
To	u_master_sram_spi/rd_status_Z[6]
Launch Clk	clk_25m:[R]
Latch Clk	clk_25m:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R13C8[0][B]	delay_rst_Z[2]/CLK
2.824	0.333	tC2Q	RF	7	R13C8[0][B]	delay_rst_Z[2]/Q
3.062	0.238	tNET	FF	1	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/I0
3.447	0.385	tINS	FR	28	R13C8[1][A]	u_master_sram_spi/rd_reg_ns_1_0_.rstn1/F
4.858	1.411	tNET	RR	1	R8C11[1][A]	u_master_sram_spi/rd_status_Z[6]/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_25m(shadow)
2.491	2.491	tCL	RR	137	PLL_L	u_pll1/pll_inst/CLKOUT
2.491	0.000	tNET	RR	1	R8C11[1][A]	u_master_sram_spi/rd_status_Z[6]/CLK
2.491	0.000	tUnc				u_master_sram_spi/rd_status_Z[6]
2.506	0.015	tHld		1	R8C11[1][A]	u_master_sram_spi/rd_status_Z[6]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 0.385, 16.266%; route: 1.649, 69.652%; tC2Q: 0.333, 14.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	delay_rst_fast_Z[3]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	delay_rst_fast_Z[3]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	delay_rst_fast_Z[3]/CLK

MPW2

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	clk_en_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	clk_en_0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	clk_en_0/CLK

MPW3

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	counter0_Z[2]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	counter0_Z[2]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	counter0_Z[2]/CLK

MPW4

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	delay_rst_Z[3]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	delay_rst_Z[3]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	delay_rst_Z[3]/CLK

MPW5

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	u_master_sram_spi/start_dl_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	u_master_sram_spi/start_dl_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	u_master_sram_spi/start_dl_Z/CLK

MPW6

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	u_master_sram_spi/err_flag_reg_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	u_master_sram_spi/err_flag_reg_0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	u_master_sram_spi/err_flag_reg_0/CLK

MPW7

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[1]/CLK

MPW8

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	u_spi_master/u_spi_master/genblk1.clock_cnt_Z[0]_Z/CLK

MPW9

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	u_master_sram_spi/r_flag_reg_0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	u_master_sram_spi/r_flag_reg_0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	u_master_sram_spi/r_flag_reg_0/CLK

MPW10

MPW Summary:

Slack:	17.864
Actual Width:	19.114
Required Width:	1.250
Type:	Low Pulse Width
Clock:	clk_25m
Objects:	u_spi_master/u_spi_master/genblk1.SS_N_MASTER[0]

Late clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk_25m(shadow)
23.377	3.377	tCL	FF	u_pll1/pll_inst/CLKOUT
23.377	0.000	tNET	FF	u_spi_master/u_spi_master/genblk1.SS_N_MASTER[0]/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
40.000	0.000			active clock edge time
40.000	0.000			clk_25m(shadow)
42.491	2.491	tCL	RR	u_pll1/pll_inst/CLKOUT
42.491	0.000	tNET	RR	u_spi_master/u_spi_master/genblk1.SS_N_MASTER[0]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
137	clkout_25m	26.172	0.000
28	rstn1	32.695	3.168
18	N_96	26.172	1.519
18	N_97	23.590	1.336
17	g0_2_0_a3_1_0	30.296	1.347
14	genblk1.c_status[2]	31.246	1.174
14	clk_en	37.711	2.163
13	genblk1.n_status37_1	33.672	1.172
12	N_95	28.738	1.336
12	genblk1.reg_toe6_0	33.239	1.683

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C12	0.500
R11C13	0.486
R9C12	0.472
R12C13	0.458
R9C13	0.431
R11C14	0.389
R9C9	0.375
R9C10	0.361
R8C12	0.361
R8C13	0.361

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_50m -period 20 -waveform {0 10} [get_ports {clk_50m}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name clk_25m -source [get_ports {clk_50m}] -master_clock clk_50m -divide_by 2 [get_nets {clkout_25m}]