Project Settings Project Name PSRAM Device Name rev_1: GOWIN-GW2AR : GW2AR_18 Implementation Name rev_1 Top Module [auto] Pipelining 1 Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 1 Disable Sequential Optimizations 0 Clock Conversion 1 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 10 1 0 - 00m:07s - 2020/5/19 15:00:42 (premap) Complete 6 2 0 0m:03s 0m:04s 230MB 2020/5/19 15:00:51 (fpga_mapper) Complete 12 9 0 0m:11s 0m:12s 257MB 2020/5/19 15:01:04 Multi-srs Generator Complete 00m:01s 2020/5/19 15:00:44 Area Summary I/O ports (io_port) 192 Non I/O Register bits (non_io_reg) 603 (3%) I/O Register bits (total_io_reg) 0 Ultra Rams 0 Block Rams (v_ram) 0 (46) Block Multipliers (dsp_used) 0 (24) LUTs (total_luts) 1083 (5%) Timing Summary Clock Name Req Freq Est Freq Slack PSRAM_Memory_Interface_Top|clk 292.1 MHz 248.3 MHz -0.604 _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0] 0.1 MHz NA NA _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1] 0.1 MHz NA NA _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock 178.6 MHz 151.8 MHz -0.988 _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock 150.0 MHz NA NA _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0] 0.1 MHz NA NA System 1638.5 MHz 1392.8 MHz -0.108 Optimizations Summary Combined Clock Conversion 3 / 3