#Build: Synplify Pro (R) Q-2020.03G-Beta1, Build 136R, May 11 2020 #install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-032 # Tue May 19 15:00:35 2020 #Implementation: rev_1 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys HDL Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Verilog Compiler, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v" (library work) @I:"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v":"E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram_memory_interface\temp\PSRAM\psram_define.v" (library work) @I:"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v":"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\psram_local_define.v" (library work) @I:"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v":"E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram_memory_interface\temp\PSRAM\psram_param.v" (library work) @I:"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\PSRAM_TOP.v":"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\psram_local_param.v" (library work) @I::"C:\Gowin\Gowin_V1.9.5.02Beta\IDE\ipcore\PSRAM\data\psram_code.v" (library work) @N:CG346 : psram_code.v(2150) | Read full_case directive. @N:CG347 : psram_code.v(2150) | Read a parallel_case directive. @W:CG286 : psram_code.v(2150) | Case statement has both a full_case directive and a default clause -- ignoring full_case directive. Verilog syntax check successful! Selecting top level module PSRAM_Memory_Interface_Top Running optimization stage 1 on OSER4 ....... Running optimization stage 1 on IDES4 ....... Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_Top _Z1 ....... Running optimization stage 1 on \~psram_lane.PSRAM_Memory_Interface_Top _Z2 ....... Running optimization stage 1 on IOBUF ....... Running optimization stage 1 on IODELAY ....... Running optimization stage 1 on ELVDS_OBUF ....... Running optimization stage 1 on OBUF ....... Running optimization stage 1 on \~psram_wd.PSRAM_Memory_Interface_Top ....... Running optimization stage 1 on \~psram_init.PSRAM_Memory_Interface_Top ....... Running optimization stage 1 on \~psram_sync.PSRAM_Memory_Interface_Top ....... Running optimization stage 1 on DLL ....... Running optimization stage 1 on DHCEN ....... Running optimization stage 1 on CLKDIV ....... Running optimization stage 1 on \~psram_top.PSRAM_Memory_Interface_Top ....... @N:CG364 : PSRAM_TOP.v(5) | Synthesizing module PSRAM_Memory_Interface_Top in library work. Running optimization stage 1 on PSRAM_Memory_Interface_Top ....... Running optimization stage 2 on PSRAM_Memory_Interface_Top ....... Running optimization stage 2 on \~psram_top.PSRAM_Memory_Interface_Top ....... Running optimization stage 2 on CLKDIV ....... Running optimization stage 2 on DHCEN ....... Running optimization stage 2 on DLL ....... Running optimization stage 2 on \~psram_sync.PSRAM_Memory_Interface_Top ....... Extracted state machine for register flag State machine has 3 reachable states with original encodings of: 00 01 10 Running optimization stage 2 on \~psram_init.PSRAM_Memory_Interface_Top ....... Running optimization stage 2 on OBUF ....... Running optimization stage 2 on ELVDS_OBUF ....... Running optimization stage 2 on IODELAY ....... Running optimization stage 2 on IOBUF ....... Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_Top _Z2 ....... Running optimization stage 2 on \~psram_lane.PSRAM_Memory_Interface_Top _Z1 ....... Running optimization stage 2 on IDES4 ....... Running optimization stage 2 on OSER4 ....... Running optimization stage 2 on \~psram_wd.PSRAM_Memory_Interface_Top ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 113MB peak: 148MB) Process took 0h:00m:04s realtime, 0h:00m:03s cputime Process completed successfully. # Tue May 19 15:00:41 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:NF107 : psram_top.v(5) | Selected library: work cell: PSRAM_Memory_Interface_Top view verilog as top level @N:NF107 : psram_top.v(5) | Selected library: work cell: PSRAM_Memory_Interface_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 19 15:00:42 2020 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: psram_memory_interface_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 21MB peak: 22MB) Process took 0h:00m:06s realtime, 0h:00m:05s cputime Process completed successfully. # Tue May 19 15:00:42 2020 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp202003syn, Build 137R, Built May 11 2020 09:06:37, @ @N: : | Running in 64-bit mode @N:NF107 : psram_top.v(5) | Selected library: work cell: PSRAM_Memory_Interface_Top view verilog as top level @N:NF107 : psram_top.v(5) | Selected library: work cell: PSRAM_Memory_Interface_Top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue May 19 15:00:44 2020 ###########################################################] Premap Report # Tue May 19 15:00:46 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @A:MF827 : | No constraint file specified. Linked File: psram_memory_interface_scck.rpt See clock summary report "E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram_memory_interface\temp\PSRAM\rev_1\psram_memory_interface_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 133MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB) Encoding state machine flag[2:0] (in view: work.\\\~psram_sync\.PSRAM_Memory_Interface_Top\ (verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Starting clock optimization phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 226MB peak: 226MB) @N:MF578 : | Incompatible asynchronous control logic preventing generated clock conversion. Finished clock optimization phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB) @W:BN117 : psram_top.v(53) | Instance u_psram_top of partition view:work.\\\~psram_top\.PSRAM_Memory_Interface_Top\ (verilog) has no references to its outputs; instance not removed. @W:BN117 : psram_top.v(53) | Instance u_psram_top of partition view:work.\\\~psram_top\.PSRAM_Memory_Interface_Top\ (verilog) has no references to its outputs; instance not removed. Finished clock optimization report phase (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 227MB) Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 227MB peak: 228MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - System 150.0 MHz 6.667 system system_clkgroup 0 0 - _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock 186.1 MHz 5.374 inferred Autoconstr_clkgroup_0 1146 1 . _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0] 186.1 MHz 5.374 derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 1 . _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1] 186.1 MHz 5.374 derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 8 1 . _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0] 186.1 MHz 5.374 derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 2 0 - _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock 150.0 MHz 6.667 inferred Autoconstr_clkgroup_2 38 0 - PSRAM_Memory_Interface_Top|clk 302.5 MHz 3.306 inferred Autoconstr_clkgroup_1 31 ================================================================================================================================================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System 0 - - - - _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock 1146 u_psram_top.clkdiv.CLKOUT(CLKDIV) u_psram_top.rd_data_valid_d.C u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4.PCLK - _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0] 8 u_psram_top.u_psram_init.read_calibration\[0\]\.VALUE[0].Q[0](dffr) u_psram_top.u_psram_wd.dq_iodelay_gen0\[0\]\.genblk1\[6\]\.iodelay.VALUE - - _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1] 8 u_psram_top.u_psram_init.read_calibration\[1\]\.VALUE[1].Q[0](dffr) u_psram_top.u_psram_wd.dq_iodelay_gen0\[1\]\.genblk1\[1\]\.iodelay.VALUE - - _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0] 2 u_psram_top.u_psram_wd.step[8:0].Q[0](dffr) u_psram_top.u_psram_wd.ck_delay\[0\]\.iodelay.VALUE - - _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock 38 u_psram_top.u_dqce_clk_x2p.CLKOUT(DHCEN) u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.mask_oser4.FCLK - - PSRAM_Memory_Interface_Top|clk 31 clk(port) u_psram_top.u_psram_sync.dll_rst.C - - =============================================================================================================================================================================================================================================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 3 non-gated/non-generated clock tree(s) driving 1131 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 18 clock pin(s) of sequential element(s) 0 instances converted, 18 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId_0_0 clk port 31 ENCRYPTED ClockId_0_1 ENCRYPTED CLKDIV 1062 ENCRYPTED ClockId_0_2 ENCRYPTED DHCEN 38 ENCRYPTED ======================================================================================= ============================================================= Gated/Generated Clocks ============================================================= Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------- ClockId_0_3 ENCRYPTED dffr 2 ENCRYPTED Derived clock on input (not legal for GCC) ClockId_0_5 ENCRYPTED dffr 8 ENCRYPTED Derived clock on input (not legal for GCC) ClockId_0_7 ENCRYPTED dffr 8 ENCRYPTED Derived clock on input (not legal for GCC) ================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram_memory_interface\temp\PSRAM\rev_1\psram_memory_interface.sap. Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 228MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 228MB) Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 228MB peak: 228MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 230MB) Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Tue May 19 15:00:51 2020 ###########################################################] Map & Optimize Report # Tue May 19 15:00:52 2020 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03G-Beta1 Install: C:\Gowin\Gowin_V1.9.5.02Beta\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-032 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1618R, Built May 14 2020 22:24:42, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 139MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 221MB peak: 221MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 226MB peak: 226MB) Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 231MB peak: 231MB) Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 236MB peak: 236MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 237MB peak: 237MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 239MB peak: 239MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:04s; Memory used current: 239MB peak: 239MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 239MB peak: 239MB) Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 239MB peak: 239MB) Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 256MB peak: 256MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s -2.62ns 1157 / 564 2 0h:00m:05s -2.62ns 1151 / 564 3 0h:00m:05s -2.62ns 1152 / 564 Timing driven replication report Added 5 Registers via timing driven replication Added 0 LUTs via timing driven replication 4 0h:00m:06s -2.62ns 1152 / 569 5 0h:00m:06s -1.96ns 1155 / 569 6 0h:00m:06s -1.84ns 1157 / 569 7 0h:00m:06s -1.84ns 1159 / 569 Timing driven replication report Added 7 Registers via timing driven replication Added 6 LUTs via timing driven replication Timing driven replication report Added 27 Registers via timing driven replication Added 27 LUTs via timing driven replication 8 0h:00m:06s -1.92ns 1189 / 603 9 0h:00m:06s -1.97ns 1190 / 603 10 0h:00m:06s -1.97ns 1190 / 603 11 0h:00m:06s -1.97ns 1190 / 603 12 0h:00m:06s -1.97ns 1190 / 603 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 256MB peak: 256MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @W:MT453 : | clock period is too long for clock _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. @W:MT453 : | clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 256MB peak: 256MB) Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 181MB peak: 257MB) Writing Analyst data base E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram_memory_interface\temp\PSRAM\rev_1\synwork\psram_memory_interface_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 255MB peak: 257MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 256MB peak: 257MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 256MB peak: 257MB) Start final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 253MB peak: 257MB) @W:MT246 : psram_code.v(2548) | Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : psram_code.v(2540) | Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : psram_code.v(2528) | Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock with period 5.60ns. Please declare a user-defined clock on net u_psram_top.clk_outz. @W:MT420 : | Found inferred clock PSRAM_Memory_Interface_Top|clk with period 3.42ns. Please declare a user-defined clock on port clk. @W:MT420 : | Found inferred clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock with period 6.67ns. Please declare a user-defined clock on net u_psram_top.clk_x2p. @N:MT615 : | Found clock _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0] with period 20000.00ns @N:MT615 : | Found clock _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0] with period 20000.00ns @N:MT615 : | Found clock _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1] with period 20000.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Tue May 19 15:01:03 2020 # Top view: PSRAM_Memory_Interface_Top Requested Frequency: 0.1 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.988 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PSRAM_Memory_Interface_Top|clk 292.1 MHz 248.3 MHz 3.424 4.028 -0.604 inferred Autoconstr_clkgroup_1 _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0] 0.1 MHz NA 20000.000 NA NA derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1] 0.1 MHz NA 20000.000 NA NA derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock 178.6 MHz 151.8 MHz 5.599 6.587 -0.988 inferred Autoconstr_clkgroup_0 _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock 150.0 MHz NA 6.667 NA NA inferred Autoconstr_clkgroup_2 _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0] 0.1 MHz NA 20000.000 NA NA derived (from _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock) Autoconstr_clkgroup_0 System 1638.5 MHz 1392.8 MHz 0.610 0.718 -0.108 system system_clkgroup ==================================================================================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 0.610 -0.108 | No paths - | No paths - | No paths - System _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock | 5.599 1.682 | No paths - | No paths - | No paths - System PSRAM_Memory_Interface_Top|clk | 3.424 2.279 | No paths - | No paths - | No paths - _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock | 5.599 -0.988 | No paths - | No paths - | No paths - _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PSRAM_Memory_Interface_Top|clk System | 3.424 1.541 | No paths - | No paths - | No paths - PSRAM_Memory_Interface_Top|clk _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PSRAM_Memory_Interface_Top|clk PSRAM_Memory_Interface_Top|clk | 3.424 -0.604 | No paths - | No paths - | No paths - ======================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PSRAM_Memory_Interface_Top|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_syn[1] PSRAM_Memory_Interface_Top|clk DFFC Q lock_cnt 0.243 -0.604 u_psram_top.u_psram_sync.lock_cnt[0] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[0] 0.243 -0.564 u_psram_top.u_psram_sync.lock_cnt[1] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[1] 0.243 -0.529 u_psram_top.u_psram_sync.lock_cnt[2] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[2] 0.243 -0.494 u_psram_top.u_psram_sync.lock_cnt[3] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[3] 0.243 -0.459 u_psram_top.u_psram_sync.lock_cnt[4] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[4] 0.243 -0.424 u_psram_top.u_psram_sync.lock_cnt[5] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[5] 0.243 -0.389 u_psram_top.u_psram_sync.lock_cnt[6] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[6] 0.243 -0.354 u_psram_top.u_psram_sync.lock_cnt[7] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[7] 0.243 -0.319 u_psram_top.u_psram_sync.lock_cnt[8] PSRAM_Memory_Interface_Top|clk DFFCE Q lock_cnt[8] 0.243 -0.284 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_cnt[15] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[15] 3.363 -0.604 u_psram_top.u_psram_sync.lock_cnt[14] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[14] 3.363 -0.569 u_psram_top.u_psram_sync.lock_cnt[13] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[13] 3.363 -0.534 u_psram_top.u_psram_sync.lock_cnt[12] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[12] 3.363 -0.499 u_psram_top.u_psram_sync.lock_cnt[11] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[11] 3.363 -0.464 u_psram_top.u_psram_sync.lock_cnt[10] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[10] 3.363 -0.429 u_psram_top.u_psram_sync.lock_cnt[9] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[9] 3.363 -0.394 u_psram_top.u_psram_sync.lock_cnt[8] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[8] 3.363 -0.359 u_psram_top.u_psram_sync.lock_cnt[7] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[7] 3.363 -0.324 u_psram_top.u_psram_sync.lock_cnt[6] PSRAM_Memory_Interface_Top|clk DFFCE D lock_cnt_s[6] 3.363 -0.289 ===================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.424 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.363 - Propagation time: 3.967 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.604 Number of logic level(s): 17 Starting point: u_psram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_psram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK The end point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.243 0.243 r - lock_cnt Net - - 0.596 - 18 u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 I0 In - 0.839 r - u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 F Out 0.549 1.388 r - lock_cnt_cry_0_RNO[0] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[0] ALU I0 In - 1.923 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[0] ALU COUT Out 0.549 2.472 r - lock_cnt_cry[0] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU CIN In - 2.472 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.035 2.507 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.507 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.035 2.542 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.542 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.035 2.577 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.577 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.035 2.612 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.612 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.035 2.647 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.647 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.035 2.682 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.682 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.035 2.717 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.717 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.035 2.752 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.752 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.035 2.787 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 2.787 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.035 2.822 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 2.822 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.035 2.857 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 2.857 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.035 2.892 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 2.892 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.035 2.927 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 2.927 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.035 2.962 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 2.962 r - u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.470 3.432 f - lock_cnt_s[15] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 3.967 f - ============================================================================================================== Total path delay (propagation time + setup) of 4.028 is 2.362(58.6%) logic and 1.666(41.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 3.424 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.363 - Propagation time: 3.932 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.569 Number of logic level(s): 16 Starting point: u_psram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_psram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK The end point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.243 0.243 r - lock_cnt Net - - 0.596 - 18 u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[1] LUT2 I0 In - 0.839 r - u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[1] LUT2 F Out 0.549 1.388 r - lock_cnt_cry_0_RNO[1] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU I0 In - 1.923 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.549 2.472 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.472 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.035 2.507 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.507 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.035 2.542 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.542 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.035 2.577 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.577 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.035 2.612 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.612 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.035 2.647 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.647 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.035 2.682 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.682 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.035 2.717 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.717 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.035 2.752 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 2.752 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.035 2.787 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 2.787 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.035 2.822 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 2.822 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.035 2.857 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 2.857 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.035 2.892 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 2.892 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.035 2.927 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 2.927 r - u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.470 3.397 f - lock_cnt_s[15] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 3.932 f - ============================================================================================================== Total path delay (propagation time + setup) of 3.993 is 2.327(58.3%) logic and 1.666(41.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 3.424 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.363 - Propagation time: 3.932 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.569 Number of logic level(s): 16 Starting point: u_psram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_psram_top.u_psram_sync.lock_cnt[14] / D The start point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK The end point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.243 0.243 r - lock_cnt Net - - 0.596 - 18 u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 I0 In - 0.839 r - u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 F Out 0.549 1.388 r - lock_cnt_cry_0_RNO[0] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[0] ALU I0 In - 1.923 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[0] ALU COUT Out 0.549 2.472 r - lock_cnt_cry[0] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU CIN In - 2.472 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.035 2.507 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.507 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.035 2.542 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.542 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.035 2.577 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.577 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.035 2.612 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.612 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.035 2.647 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.647 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.035 2.682 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.682 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.035 2.717 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.717 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.035 2.752 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.752 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.035 2.787 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 2.787 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.035 2.822 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 2.822 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.035 2.857 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 2.857 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.035 2.892 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 2.892 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.035 2.927 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 2.927 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU SUM Out 0.470 3.397 f - lock_cnt_s[14] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt[14] DFFCE D In - 3.932 f - ============================================================================================================== Total path delay (propagation time + setup) of 3.993 is 2.327(58.3%) logic and 1.666(41.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 3.424 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.363 - Propagation time: 3.927 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.564 Number of logic level(s): 17 Starting point: u_psram_top.u_psram_sync.lock_cnt[0] / Q Ending point: u_psram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK The end point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_cnt[0] DFFCE Q Out 0.243 0.243 r - lock_cnt[0] Net - - 0.535 - 2 u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 I1 In - 0.778 r - u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[0] LUT2 F Out 0.570 1.348 r - lock_cnt_cry_0_RNO[0] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[0] ALU I0 In - 1.883 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[0] ALU COUT Out 0.549 2.432 r - lock_cnt_cry[0] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU CIN In - 2.432 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[1] ALU COUT Out 0.035 2.467 r - lock_cnt_cry[1] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU CIN In - 2.467 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.035 2.502 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.502 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.035 2.537 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.537 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.035 2.572 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.572 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.035 2.607 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.607 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.035 2.642 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.642 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.035 2.677 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.677 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.035 2.712 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.712 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.035 2.747 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 2.747 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.035 2.782 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 2.782 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.035 2.817 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 2.817 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.035 2.852 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 2.852 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.035 2.887 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 2.887 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.035 2.922 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 2.922 r - u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.470 3.392 f - lock_cnt_s[15] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 3.927 f - ============================================================================================================== Total path delay (propagation time + setup) of 3.988 is 2.383(59.8%) logic and 1.605(40.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 3.424 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.363 - Propagation time: 3.897 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.534 Number of logic level(s): 15 Starting point: u_psram_top.u_psram_sync.lock_syn[1] / Q Ending point: u_psram_top.u_psram_sync.lock_cnt[15] / D The start point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK The end point is clocked by PSRAM_Memory_Interface_Top|clk [rising] (rise=0.000 fall=1.712 period=3.424) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- u_psram_top.u_psram_sync.lock_syn[1] DFFC Q Out 0.243 0.243 r - lock_cnt Net - - 0.596 - 18 u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[2] LUT2 I0 In - 0.839 r - u_psram_top.u_psram_sync.lock_cnt_cry_0_RNO[2] LUT2 F Out 0.549 1.388 r - lock_cnt_cry_0_RNO[2] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU I0 In - 1.923 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[2] ALU COUT Out 0.549 2.472 r - lock_cnt_cry[2] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU CIN In - 2.472 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[3] ALU COUT Out 0.035 2.507 r - lock_cnt_cry[3] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU CIN In - 2.507 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[4] ALU COUT Out 0.035 2.542 r - lock_cnt_cry[4] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU CIN In - 2.542 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[5] ALU COUT Out 0.035 2.577 r - lock_cnt_cry[5] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU CIN In - 2.577 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[6] ALU COUT Out 0.035 2.612 r - lock_cnt_cry[6] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU CIN In - 2.612 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[7] ALU COUT Out 0.035 2.647 r - lock_cnt_cry[7] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU CIN In - 2.647 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[8] ALU COUT Out 0.035 2.682 r - lock_cnt_cry[8] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU CIN In - 2.682 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[9] ALU COUT Out 0.035 2.717 r - lock_cnt_cry[9] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU CIN In - 2.717 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[10] ALU COUT Out 0.035 2.752 r - lock_cnt_cry[10] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU CIN In - 2.752 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[11] ALU COUT Out 0.035 2.787 r - lock_cnt_cry[11] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU CIN In - 2.787 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[12] ALU COUT Out 0.035 2.822 r - lock_cnt_cry[12] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU CIN In - 2.822 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[13] ALU COUT Out 0.035 2.857 r - lock_cnt_cry[13] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU CIN In - 2.857 r - u_psram_top.u_psram_sync.lock_cnt_cry_0[14] ALU COUT Out 0.035 2.892 r - lock_cnt_cry[14] Net - - 0.000 - 1 u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU CIN In - 2.892 r - u_psram_top.u_psram_sync.lock_cnt_s_0[15] ALU SUM Out 0.470 3.362 f - lock_cnt_s[15] Net - - 0.535 - 1 u_psram_top.u_psram_sync.lock_cnt[15] DFFCE D In - 3.897 f - ============================================================================================================== Total path delay (propagation time + setup) of 3.958 is 2.292(57.9%) logic and 1.666(42.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.rd_data_d[26] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFC Q rd_data_d[26] 0.243 -0.988 u_psram_top.rd_data_d[15] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFC Q rd_data_d[15] 0.243 -0.967 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[1] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE Q check_cnt_0[1] 0.243 -0.902 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[0] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE Q check_cnt_0[0] 0.243 -0.881 u_psram_top.rd_data_d[27] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFC Q rd_data_d[27] 0.243 -0.880 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[7] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE Q check_cnt_0[7] 0.243 -0.794 u_psram_top.rd_data_d[29] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFC Q rd_data_d[29] 0.243 -0.789 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[8] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE Q check_cnt_0[8] 0.243 -0.703 u_psram_top.u_psram_init.init_calib_d2_fast _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE Q init_calib_fast 0.243 -0.531 u_psram_top.rd_data_valid_d_fast _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFC Q rd_data_valid_d_fast 0.243 -0.491 ================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[0] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[1] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[2] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[3] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[4] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[5] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[6] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[7] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[8] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[9] _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock DFFCE CE check_cnte_0 5.538 -0.988 ========================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 6.526 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.988 Number of logic level(s): 6 Starting point: u_psram_top.rd_data_d[26] / Q Ending point: u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[0] / CE The start point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.rd_data_d[26] DFFC Q Out 0.243 0.243 r - rd_data_d[26] Net - - 0.535 - 4 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 I1 In - 0.778 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 F Out 0.570 1.348 r - un1_rd_data_valid_3_29_0_a4_3 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 S0 In - 1.883 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 O Out 0.269 2.152 r - N_212 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 I0 In - 2.687 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 F Out 0.549 3.236 r - un1_rd_data_valid_3_6 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 I3 In - 3.637 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 F Out 0.371 4.008 f - check_cntlde_N_6L9 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 I0 In - 4.409 f - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 F Out 0.549 4.958 r - check_cntlde_1_1 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 I1 In - 5.360 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 F Out 0.570 5.930 r - check_cnte_0 Net - - 0.596 - 11 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[0] DFFCE CE In - 6.526 r - ================================================================================================================================================= Total path delay (propagation time + setup) of 6.587 is 3.182(48.3%) logic and 3.405(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 6.526 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.988 Number of logic level(s): 6 Starting point: u_psram_top.rd_data_d[26] / Q Ending point: u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[1] / CE The start point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.rd_data_d[26] DFFC Q Out 0.243 0.243 r - rd_data_d[26] Net - - 0.535 - 4 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 I1 In - 0.778 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 F Out 0.570 1.348 r - un1_rd_data_valid_3_29_0_a4_3 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 S0 In - 1.883 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 O Out 0.269 2.152 r - N_212 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 I0 In - 2.687 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 F Out 0.549 3.236 r - un1_rd_data_valid_3_6 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 I3 In - 3.637 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 F Out 0.371 4.008 f - check_cntlde_N_6L9 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 I0 In - 4.409 f - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 F Out 0.549 4.958 r - check_cntlde_1_1 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 I1 In - 5.360 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 F Out 0.570 5.930 r - check_cnte_0 Net - - 0.596 - 11 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[1] DFFCE CE In - 6.526 r - ================================================================================================================================================= Total path delay (propagation time + setup) of 6.587 is 3.182(48.3%) logic and 3.405(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 6.526 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.988 Number of logic level(s): 6 Starting point: u_psram_top.rd_data_d[26] / Q Ending point: u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[2] / CE The start point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.rd_data_d[26] DFFC Q Out 0.243 0.243 r - rd_data_d[26] Net - - 0.535 - 4 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 I1 In - 0.778 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 F Out 0.570 1.348 r - un1_rd_data_valid_3_29_0_a4_3 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 S0 In - 1.883 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 O Out 0.269 2.152 r - N_212 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 I0 In - 2.687 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 F Out 0.549 3.236 r - un1_rd_data_valid_3_6 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 I3 In - 3.637 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 F Out 0.371 4.008 f - check_cntlde_N_6L9 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 I0 In - 4.409 f - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 F Out 0.549 4.958 r - check_cntlde_1_1 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 I1 In - 5.360 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 F Out 0.570 5.930 r - check_cnte_0 Net - - 0.596 - 11 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[2] DFFCE CE In - 6.526 r - ================================================================================================================================================= Total path delay (propagation time + setup) of 6.587 is 3.182(48.3%) logic and 3.405(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 6.526 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.988 Number of logic level(s): 6 Starting point: u_psram_top.rd_data_d[26] / Q Ending point: u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[3] / CE The start point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.rd_data_d[26] DFFC Q Out 0.243 0.243 r - rd_data_d[26] Net - - 0.535 - 4 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 I1 In - 0.778 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 F Out 0.570 1.348 r - un1_rd_data_valid_3_29_0_a4_3 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 S0 In - 1.883 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 O Out 0.269 2.152 r - N_212 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 I0 In - 2.687 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 F Out 0.549 3.236 r - un1_rd_data_valid_3_6 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 I3 In - 3.637 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 F Out 0.371 4.008 f - check_cntlde_N_6L9 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 I0 In - 4.409 f - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 F Out 0.549 4.958 r - check_cntlde_1_1 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 I1 In - 5.360 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 F Out 0.570 5.930 r - check_cnte_0 Net - - 0.596 - 11 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[3] DFFCE CE In - 6.526 r - ================================================================================================================================================= Total path delay (propagation time + setup) of 6.587 is 3.182(48.3%) logic and 3.405(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 6.526 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.988 Number of logic level(s): 6 Starting point: u_psram_top.rd_data_d[26] / Q Ending point: u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[4] / CE The start point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.rd_data_d[26] DFFC Q Out 0.243 0.243 r - rd_data_d[26] Net - - 0.535 - 4 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 I1 In - 0.778 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4_3 LUT4 F Out 0.570 1.348 r - un1_rd_data_valid_3_29_0_a4_3 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 S0 In - 1.883 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_29_0_a4 MUX2_LUT5 O Out 0.269 2.152 r - N_212 Net - - 0.535 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 I0 In - 2.687 r - u_psram_top.u_psram_init.read_calibration\[1\]\.un1_rd_data_valid_3_6 LUT4 F Out 0.549 3.236 r - un1_rd_data_valid_3_6 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 I3 In - 3.637 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_N_6L9 LUT4 F Out 0.371 4.008 f - check_cntlde_N_6L9 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 I0 In - 4.409 f - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde_1_1 LUT4 F Out 0.549 4.958 r - check_cntlde_1_1 Net - - 0.401 - 1 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 I1 In - 5.360 r - u_psram_top.u_psram_init.read_calibration\[1\]\.check_cntlde LUT4 F Out 0.570 5.930 r - check_cnte_0 Net - - 0.596 - 11 u_psram_top.u_psram_init.read_calibration\[1\]\.check_cnt[4] DFFCE CE In - 6.526 r - ================================================================================================================================================= Total path delay (propagation time + setup) of 6.587 is 3.182(48.3%) logic and 3.405(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------ u_psram_top.u_dqce_clk_x2p System DHCEN CLKOUT clk_x2p_i 0.000 -0.108 u_psram_top.clkdiv System CLKDIV CLKOUT clk_out 0.000 1.682 u_psram_top.u_dll System DLL LOCK dll_lock 0.000 2.279 u_psram_top.u_dll System DLL STEP[0] dll_step[0] 0.000 2.924 u_psram_top.u_dll System DLL STEP[1] dll_step[1] 0.000 2.959 u_psram_top.u_dll System DLL STEP[2] dll_step[2] 0.000 2.994 u_psram_top.u_dll System DLL STEP[3] dll_step[3] 0.000 3.029 u_psram_top.u_dll System DLL STEP[4] dll_step[4] 0.000 3.064 u_psram_top.u_dll System DLL STEP[5] dll_step[5] 0.000 3.099 u_psram_top.u_dll System DLL STEP[6] dll_step[6] 0.000 3.134 ====================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------- u_psram_top.clkdiv System CLKDIV HCLKIN clk_x2p_i 0.610 -0.108 u_psram_top.u_dll System DLL CLKIN clk_x2p_i 0.610 -0.108 u_psram_top.rd_data_d[0] System DFFC D rd_data_d_3[0] 5.538 1.682 u_psram_top.rd_data_d[1] System DFFC D rd_data_d_3[1] 5.538 1.682 u_psram_top.rd_data_d[2] System DFFC D rd_data_d_3[2] 5.538 1.682 u_psram_top.rd_data_d[3] System DFFC D rd_data_d_3[3] 5.538 1.682 u_psram_top.rd_data_d[4] System DFFC D rd_data_d_3[4] 5.538 1.682 u_psram_top.rd_data_d[5] System DFFC D rd_data_d_3[5] 5.538 1.682 u_psram_top.rd_data_d[6] System DFFC D rd_data_d_3[6] 5.538 1.682 u_psram_top.rd_data_d[7] System DFFC D rd_data_d_3[7] 5.538 1.682 ======================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.610 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.610 - Propagation time: 0.718 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.108 Number of logic level(s): 0 Starting point: u_psram_top.u_dqce_clk_x2p / CLKOUT Ending point: u_psram_top.clkdiv / HCLKIN The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- u_psram_top.u_dqce_clk_x2p DHCEN CLKOUT Out 0.000 0.000 r - clk_x2p_i Net - - 0.718 - 40 u_psram_top.clkdiv CLKDIV HCLKIN In - 0.718 r - ============================================================================================= Total path delay (propagation time + setup) of 0.718 is 0.000(0.0%) logic and 0.718(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.610 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.610 - Propagation time: 0.718 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.108 Number of logic level(s): 0 Starting point: u_psram_top.u_dqce_clk_x2p / CLKOUT Ending point: u_psram_top.u_dll / CLKIN The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- u_psram_top.u_dqce_clk_x2p DHCEN CLKOUT Out 0.000 0.000 r - clk_x2p_i Net - - 0.718 - 40 u_psram_top.u_dll DLL CLKIN In - 0.718 r - ============================================================================================ Total path delay (propagation time + setup) of 0.718 is 0.000(0.0%) logic and 0.718(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 3.856 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.682 Number of logic level(s): 2 Starting point: u_psram_top.clkdiv / CLKOUT Ending point: u_psram_top.rd_data_d[8] / D The start point is clocked by System [rising] The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out Net - - 2.607 - 629 u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4 IDES4 PCLK In - 2.607 r - u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[0\]\.u_ides4 IDES4 Q3 Out 0.165 2.772 r - rd_data_d0[8] Net - - 0.535 - 2 u_psram_top.rd_data_d_3[8] LUT2 I0 In - 3.307 r - u_psram_top.rd_data_d_3[8] LUT2 F Out 0.549 3.856 r - rd_data_d_3[8] Net - - 0.000 - 1 u_psram_top.rd_data_d[8] DFFC D In - 3.856 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 3.917 is 0.775(19.8%) logic and 3.142(80.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 3.856 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.682 Number of logic level(s): 2 Starting point: u_psram_top.clkdiv / CLKOUT Ending point: u_psram_top.rd_data_d[11] / D The start point is clocked by System [rising] The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out Net - - 2.607 - 629 u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[3\]\.u_ides4 IDES4 PCLK In - 2.607 r - u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[3\]\.u_ides4 IDES4 Q3 Out 0.165 2.772 r - rd_data_d0[11] Net - - 0.535 - 2 u_psram_top.rd_data_d_3[11] LUT2 I0 In - 3.307 r - u_psram_top.rd_data_d_3[11] LUT2 F Out 0.549 3.856 r - rd_data_d_3[11] Net - - 0.000 - 1 u_psram_top.rd_data_d[11] DFFC D In - 3.856 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 3.917 is 0.775(19.8%) logic and 3.142(80.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.599 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.538 - Propagation time: 3.856 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 1.682 Number of logic level(s): 2 Starting point: u_psram_top.clkdiv / CLKOUT Ending point: u_psram_top.rd_data_d[14] / D The start point is clocked by System [rising] The end point is clocked by _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock [rising] (rise=0.000 fall=2.799 period=5.599) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------- u_psram_top.clkdiv CLKDIV CLKOUT Out 0.000 0.000 r - clk_out Net - - 2.607 - 629 u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4 IDES4 PCLK In - 2.607 r - u_psram_top.u_psram_wd.data_lane_gen\[1\]\.u_psram_lane.iserdes_gen\[6\]\.u_ides4 IDES4 Q3 Out 0.165 2.772 r - rd_data_d0[14] Net - - 0.535 - 2 u_psram_top.rd_data_d_3[14] LUT2 I0 In - 3.307 r - u_psram_top.rd_data_d_3[14] LUT2 F Out 0.549 3.856 r - rd_data_d_3[14] Net - - 0.000 - 1 u_psram_top.rd_data_d[14] DFFC D In - 3.856 r - ==================================================================================================================================================== Total path delay (propagation time + setup) of 3.917 is 0.775(19.8%) logic and 3.142(80.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 254MB peak: 257MB) Finished timing report (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 254MB peak: 257MB) --------------------------------------- Resource Usage Report for PSRAM_Memory_Interface_Top Mapping to part: gw2ar_18elqfp144-8 Cell usage: ALU 129 uses CLKDIV 1 use DFF 72 uses DFFC 302 uses DFFCE 219 uses DFFP 9 uses DFFPE 1 use DHCEN 1 use DLL 1 use GSR 1 use IDES4 16 uses INV 5 uses IODELAY 18 uses MUX2_LUT5 1 use OSER4 22 uses RAM16SDP4 18 uses LUT2 435 uses LUT3 248 uses LUT4 400 uses I/O ports: 192 I/O primitives: 22 ELVDS_OBUF 2 uses IOBUF 18 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 603 of 15552 (3%) Total load per clock: _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock: 628 PSRAM_Memory_Interface_Top|clk: 31 _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock: 38 _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0]: 2 _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0]: 8 _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1]: 8 @S |Mapping Summary: Total Luts in terms of LUT4: LUT4 + LUT5 * 2 + LUT6 * 4 + LUT7 * 8 + LUT8 * 16 + MUX2 * 1 + MUX4 * 2 + MUX8 * 3 + MUX16 * 4 + MUX32 * 5 Total LUTs: 1083 (5%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 84MB peak: 257MB) Process took 0h:00m:12s realtime, 0h:00m:11s cputime # Tue May 19 15:01:04 2020 ###########################################################]