@W: MT453 |clock period is too long for clock _~psram_wd_PSRAM_Memory_Interface_Top_|step_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[0]_VALUE_derived_clock[0], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. 
@W: MT453 |clock period is too long for clock _~psram_init_PSRAM_Memory_Interface_Top_|read_calibration[1]_VALUE_derived_clock[1], changing period from 66667.0 to 20000.0 ns, rise from 0.0 ns to 0.0 ns, and fall from 33333.5 ns to 10000.0 ns. 
@W: MT246 :"c:\gowin\gowin_v1.9.5.02beta\ide\ipcore\psram\data\psram_code.v":2548:8:2548:13|Blackbox CLKDIV is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\gowin\gowin_v1.9.5.02beta\ide\ipcore\psram\data\psram_code.v":2540:7:2540:20|Blackbox DHCEN is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\gowin\gowin_v1.9.5.02beta\ide\ipcore\psram\data\psram_code.v":2528:2:2528:6|Blackbox DLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_out_inferred_clock with period 5.60ns. Please declare a user-defined clock on net u_psram_top.clk_outz.
@W: MT420 |Found inferred clock PSRAM_Memory_Interface_Top|clk with period 3.42ns. Please declare a user-defined clock on port clk.
@W: MT420 |Found inferred clock _~psram_top_PSRAM_Memory_Interface_Top_|clk_x2p_inferred_clock with period 6.67ns. Please declare a user-defined clock on net u_psram_top.clk_x2p.
