Timing Messages

Report Title Gowin Timing Analysis Report
Design File E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\impl\synthesize\rev_1\psram_ref_design.vm
Physical Constraints File E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram.cst
Timing Constraint File E:\IP_verify\19.5.02\IPWeb\Gowin_PSRAM_Memory_Interface_refDesign\project\src\psram.sdc
GOWIN version V1.9.5.02Beta
Part Number GW2AR-LV18EQ144PC8/I7
Created Time Tue May 19 15:08:03 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 0.95V 85C
Hold Delay Model Fast 1.05V 0C
Numbers of Paths Analyzed 2524
Numbers of Endpoints Analyzed 3712
Numbers of Falling Endpoints 1
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_x1 Base 10.000 100.000 0.000 5.000 clk_x1
clk_x2 Base 5.000 200.000 0.000 2.500 u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
u_PLL/CLKIN.default_clk Base 20.000 50.000 0.000 10.000
u_PLL/CLKOUT.default_gen_clk Generated 6.250 160.000 0.000 3.125 u_PLL/CLKIN.default_clk
u_PLL/CLKOUTP.default_gen_clk Generated 6.250 160.000 0.000 3.125 u_PLL/CLKIN.default_clk
u_PLL/CLKOUTD.default_gen_clk Generated 12.500 80.000 0.000 6.250 u_PLL/CLKIN.default_clk
u_PLL/CLKOUTD3.default_gen_clk Generated 18.750 53.333 0.000 9.375 u_PLL/CLKIN.default_clk

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 100.000(MHz) 148.368(MHz) 5 TOP

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of u_PLL/CLKIN.default_clk!

No timing paths to get frequency of u_PLL/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_PLL/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_PLL/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_PLL/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_x1 Setup 0.000 0
clk_x1 Hold 0.000 0
clk_x2 Setup 0.000 0
clk_x2 Hold 0.000 0
u_PLL/CLKIN.default_clk Setup 0.000 0
u_PLL/CLKIN.default_clk Hold 0.000 0
u_PLL/CLKOUT.default_gen_clk Setup 0.000 0
u_PLL/CLKOUT.default_gen_clk Hold 0.000 0
u_PLL/CLKOUTP.default_gen_clk Setup 0.000 0
u_PLL/CLKOUTP.default_gen_clk Hold 0.000 0
u_PLL/CLKOUTD.default_gen_clk Setup 0.000 0
u_PLL/CLKOUTD.default_gen_clk Hold 0.000 0
u_PLL/CLKOUTD3.default_gen_clk Setup 0.000 0
u_PLL/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 1.539 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[8]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.227
2 1.574 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[7]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.191
3 1.609 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[6]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.156
4 1.645 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[5]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.121
5 1.680 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[4]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.086
6 1.712 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 2.129
7 1.715 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[3]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.051
8 1.750 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[2]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 4.015
9 1.780 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 2.062
10 1.780 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 2.062
11 1.785 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[1]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 3.980
12 1.789 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 2.053
13 1.821 u_psram_top/u_psram_top/u_dll/CLKIN u_psram_top/u_psram_top/u_psram_wd/step_Z[0]/D clk_x2:[R] clk_x1:[R] 5.000 -1.201 3.945
14 1.987 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.855
15 1.987 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.855
16 1.993 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.849
17 1.996 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.846
18 2.074 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.767
19 2.285 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.557
20 2.285 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.557
21 2.325 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.517
22 2.325 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.517
23 2.334 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.508
24 2.372 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.470
25 2.533 u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB clk_x1:[R] clk_x2:[R] 5.000 0.758 1.309

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.194 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/WREA clk_x1:[R] clk_x1:[R] 0.000 0.000 0.335
2 0.194 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_2/WREA clk_x1:[R] clk_x1:[R] 0.000 0.000 0.335
3 0.194 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/WREA clk_x1:[R] clk_x1:[R] 0.000 0.000 0.335
4 0.194 u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/WREA clk_x1:[R] clk_x1:[R] 0.000 0.000 0.335
5 0.225 u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/DI16 clk_x1:[R] clk_x1:[R] 0.000 0.000 0.474
6 0.307 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[8]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[9]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.318
7 0.307 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[18]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[19]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.318
8 0.307 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/fixed_32cs.wr_en_delay_all[7]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.318
9 0.307 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[11]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.318
10 0.307 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_Z[2]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_d_Z[2]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.318
11 0.307 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[13]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.318
12 0.310 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[16]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[17]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.321
13 0.310 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[0]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.321
14 0.310 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[20]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[21]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.321
15 0.310 u_test/sw_syn_Z[1]/Q u_test/sw_syn_Z[2]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.321
16 0.310 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[3]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[4]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.321
17 0.312 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[5]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[6]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.323
18 0.312 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[49]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/q9_Z[2]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.323
19 0.314 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[6]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.325
20 0.314 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[4]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.325
21 0.314 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[5]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[6]/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.325
22 0.327 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[2]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1/WAD2 clk_x1:[R] clk_x1:[R] 0.000 0.000 0.339
23 0.327 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.wr_ptr[1]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_mask.mem_mask_mem_mask_0_2/WAD1 clk_x1:[R] clk_x1:[R] 0.000 0.000 0.339
24 0.330 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[0]/Q u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1/WAD0 clk_x1:[R] clk_x1:[R] 0.000 0.000 0.342
25 0.335 u_la0_top/u_ao_mem_ctrl/data_reg_Z[33]/Q u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/DI15 clk_x1:[R] clk_x1:[R] 0.000 0.000 0.584

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 3.447 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.290
2 3.447 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET clk_x1:[F] clk_x1:[R] 5.000 0.028 1.290
3 3.654 u_la0_top/rst_ao_Z/Q u_la0_top/triger_level_cnt_Z[2]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.083
4 3.654 u_la0_top/rst_ao_Z/Q u_la0_top/triger_level_cnt_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.083
5 3.654 u_la0_top/rst_ao_Z/Q u_la0_top/triger_level_cnt_Z[3]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.083
6 3.654 u_la0_top/rst_ao_Z/Q u_la0_top/triger_level_cnt_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.083
7 3.660 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.077
8 3.660 u_la0_top/rst_ao_Z/Q u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.077
9 3.660 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.077
10 3.660 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel[3]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.077
11 3.660 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_dly_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.077
12 3.666 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.071
13 3.666 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.071
14 3.666 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.071
15 3.666 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.071
16 3.666 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.071
17 3.666 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.071
18 3.677 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.060
19 3.677 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.060
20 3.683 u_la0_top/rst_ao_Z/Q u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.054
21 3.690 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.048
22 3.690 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.048
23 3.695 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 1.042
24 3.861 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 0.876
25 3.903 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR clk_x1:[F] clk_x1:[R] 5.000 0.028 0.834

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 5.385 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.585
2 5.399 u_la0_top/rst_ao_Z/Q u_la0_top/trigger_seq_start_Z/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.599
3 5.399 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.599
4 5.399 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_dly_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.599
5 5.399 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.599
6 5.399 u_la0_top/rst_ao_Z/Q u_la0_top/capture_end_dly_Z/PRESET clk_x1:[F] clk_x1:[R] -5.000 0.011 0.599
7 5.405 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.605
8 5.408 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.608
9 5.408 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.608
10 5.408 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.608
11 5.408 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.608
12 5.408 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.608
13 5.408 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_syn_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.608
14 5.411 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.611
15 5.411 u_la0_top/rst_ao_Z/Q u_la0_top/internal_reg_start_syn_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.611
16 5.411 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.611
17 5.411 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.611
18 5.411 u_la0_top/rst_ao_Z/Q u_la0_top/capture_window_sel_Z[2]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.611
19 5.522 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.722
20 5.524 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.724
21 5.524 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.724
22 5.525 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.725
23 5.525 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.725
24 5.530 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.730
25 5.530 u_la0_top/rst_ao_Z/Q u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR clk_x1:[F] clk_x1:[R] -5.000 0.011 0.730

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/rd_data_d_Z[54]
2 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/rd_data_d_Z[56]
3 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/rd_data_d_Z[60]
4 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/rd_data_d_Z[43]
5 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/rd_data_d_Z[29]
6 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/rd_data_d_Z[7]
7 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[42]
8 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.data_mask_d[21]
9 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[6]
10 3.674 4.674 1.000 Low Pulse Width clk_x1 u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[5]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 1.539
Data Arrival Time 9.227
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[8]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
8.581 0.035 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/COUT
8.581 0.000 tNET FF 2 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/CIN
8.616 0.035 tINS FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/COUT
8.616 0.000 tNET FF 2 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/CIN
8.651 0.035 tINS FF 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/COUT
8.651 0.000 tNET FF 2 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/CIN
8.686 0.035 tINS FF 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/COUT
8.686 0.000 tNET FF 2 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[6]/CIN
8.721 0.035 tINS FF 1 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[6]/COUT
8.721 0.000 tNET FF 2 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[7]/CIN
8.757 0.035 tINS FF 1 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[7]/COUT
8.757 0.000 tNET FF 2 R27C44[0][A] u_psram_top/u_psram_top/u_psram_wd/step_s_0[8]/CIN
9.227 0.470 tINS FF 1 R27C44[0][A] u_psram_top/u_psram_top/u_psram_wd/step_s_0[8]/SUM
9.227 0.000 tNET FF 1 R27C44[0][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[8]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C44[0][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[8]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[8]
10.766 -0.035 tSu 1 R27C44[0][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[8]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.940, 45.900%; route: 1.844, 43.635%; tC2Q: 0.442, 10.465%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path2

Path Summary:

Slack 1.574
Data Arrival Time 9.191
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[7]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
8.581 0.035 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/COUT
8.581 0.000 tNET FF 2 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/CIN
8.616 0.035 tINS FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/COUT
8.616 0.000 tNET FF 2 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/CIN
8.651 0.035 tINS FF 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/COUT
8.651 0.000 tNET FF 2 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/CIN
8.686 0.035 tINS FF 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/COUT
8.686 0.000 tNET FF 2 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[6]/CIN
8.721 0.035 tINS FF 1 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[6]/COUT
8.721 0.000 tNET FF 2 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[7]/CIN
9.191 0.470 tINS FF 1 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[7]/SUM
9.191 0.000 tNET FF 1 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[7]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[7]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[7]
10.766 -0.035 tSu 1 R27C43[2][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[7]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.905, 45.445%; route: 1.844, 44.002%; tC2Q: 0.442, 10.553%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path3

Path Summary:

Slack 1.609
Data Arrival Time 9.156
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[6]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
8.581 0.035 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/COUT
8.581 0.000 tNET FF 2 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/CIN
8.616 0.035 tINS FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/COUT
8.616 0.000 tNET FF 2 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/CIN
8.651 0.035 tINS FF 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/COUT
8.651 0.000 tNET FF 2 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/CIN
8.686 0.035 tINS FF 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/COUT
8.686 0.000 tNET FF 2 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[6]/CIN
9.156 0.470 tINS FF 1 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[6]/SUM
9.156 0.000 tNET FF 1 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[6]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[6]
10.766 -0.035 tSu 1 R27C43[2][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[6]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.870, 44.983%; route: 1.844, 44.374%; tC2Q: 0.442, 10.643%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path4

Path Summary:

Slack 1.645
Data Arrival Time 9.121
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[5]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
8.581 0.035 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/COUT
8.581 0.000 tNET FF 2 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/CIN
8.616 0.035 tINS FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/COUT
8.616 0.000 tNET FF 2 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/CIN
8.651 0.035 tINS FF 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/COUT
8.651 0.000 tNET FF 2 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/CIN
9.121 0.470 tINS FF 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[5]/SUM
9.121 0.000 tNET FF 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[5]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[5]
10.766 -0.035 tSu 1 R27C43[1][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[5]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.834, 44.513%; route: 1.844, 44.753%; tC2Q: 0.442, 10.734%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path5

Path Summary:

Slack 1.680
Data Arrival Time 9.086
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[4]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
8.581 0.035 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/COUT
8.581 0.000 tNET FF 2 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/CIN
8.616 0.035 tINS FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/COUT
8.616 0.000 tNET FF 2 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/CIN
9.086 0.470 tINS FF 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[4]/SUM
9.086 0.000 tNET FF 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[4]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[4]
10.766 -0.035 tSu 1 R27C43[1][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[4]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.799, 44.035%; route: 1.844, 45.139%; tC2Q: 0.442, 10.826%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path6

Path Summary:

Slack 1.712
Data Arrival Time 3.330
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.330 1.897 tNET FF 1 IOR3[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR3[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4
5.042 0.000 tSu 1 IOR3[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.897, 89.105%; tC2Q: 0.232, 10.895%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path7

Path Summary:

Slack 1.715
Data Arrival Time 9.051
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[3]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
8.581 0.035 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/COUT
8.581 0.000 tNET FF 2 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/CIN
9.051 0.470 tINS FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[3]/SUM
9.051 0.000 tNET FF 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[3]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[3]
10.766 -0.035 tSu 1 R27C43[0][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[3]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.764, 43.549%; route: 1.844, 45.531%; tC2Q: 0.442, 10.920%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path8

Path Summary:

Slack 1.750
Data Arrival Time 9.015
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[2]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.545 0.035 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/COUT
8.545 0.000 tNET FF 2 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/CIN
9.015 0.470 tINS FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[2]/SUM
9.015 0.000 tNET FF 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[2]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[2]
10.766 -0.035 tSu 1 R27C43[0][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[2]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.729, 43.054%; route: 1.844, 45.930%; tC2Q: 0.442, 11.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path9

Path Summary:

Slack 1.780
Data Arrival Time 3.262
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.262 1.830 tNET FF 1 IOR5[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR5[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4
5.042 0.000 tSu 1 IOR5[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.830, 88.748%; tC2Q: 0.232, 11.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path10

Path Summary:

Slack 1.780
Data Arrival Time 3.262
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.262 1.830 tNET FF 1 IOR5[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR5[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4
5.042 0.000 tSu 1 IOR5[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.830, 88.748%; tC2Q: 0.232, 11.252%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path11

Path Summary:

Slack 1.785
Data Arrival Time 8.980
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[1]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.510 0.035 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/COUT
8.510 0.000 tNET FF 2 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/CIN
8.980 0.470 tINS FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[1]/SUM
8.980 0.000 tNET FF 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[1]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[1]
10.766 -0.035 tSu 1 R27C42[2][B] u_psram_top/u_psram_top/u_psram_wd/step_Z[1]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.694, 42.550%; route: 1.844, 46.336%; tC2Q: 0.442, 11.113%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path12

Path Summary:

Slack 1.789
Data Arrival Time 3.253
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.253 1.821 tNET FF 1 IOR4[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR4[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4
5.042 0.000 tSu 1 IOR4[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.821, 88.698%; tC2Q: 0.232, 11.302%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path13

Path Summary:

Slack 1.821
Data Arrival Time 8.945
Data Required Time 10.766
From u_psram_top/u_psram_top/u_dll
To u_psram_top/u_psram_top/u_psram_wd/step_Z[0]
Launch Clk clk_x2:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 8 DLL_BR u_psram_top/u_psram_top/u_dll/CLKIN
5.835 0.393 tINS RF 1 DLL_BR u_psram_top/u_psram_top/u_dll/STEP0
7.680 1.844 tNET FF 2 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/I0
8.229 0.549 tINS FR 1 R27C41[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_1_0/COUT
8.229 0.000 tNET RR 2 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/CIN
8.264 0.035 tINS RF 1 R27C41[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_2_0/COUT
8.264 0.000 tNET FF 2 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/CIN
8.299 0.035 tINS FF 1 R27C41[2][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_3_0/COUT
8.299 0.000 tNET FF 2 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/CIN
8.334 0.035 tINS FF 1 R27C41[2][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_4_0/COUT
8.334 0.000 tNET FF 2 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/CIN
8.369 0.035 tINS FF 1 R27C42[0][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_5_0/COUT
8.369 0.000 tNET FF 2 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/CIN
8.405 0.035 tINS FF 1 R27C42[0][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_6_0/COUT
8.405 0.000 tNET FF 2 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/CIN
8.440 0.035 tINS FF 1 R27C42[1][A] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_7_0/COUT
8.440 0.000 tNET FF 2 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/CIN
8.475 0.035 tINS FF 1 R27C42[1][B] u_psram_top/u_psram_top/u_psram_wd/un1_step_cry_8_0/COUT
8.475 0.000 tNET FF 2 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/CIN
8.945 0.470 tINS FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_cry_0[0]/SUM
8.945 0.000 tNET FF 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[0]/CLK
10.801 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/step_Z[0]
10.766 -0.035 tSu 1 R27C42[2][A] u_psram_top/u_psram_top/u_psram_wd/step_Z[0]

Path Statistics:

Clock Skew 1.201
Setup Relationship 5.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 1.658, 42.038%; route: 1.844, 46.750%; tC2Q: 0.442, 11.212%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path14

Path Summary:

Slack 1.987
Data Arrival Time 3.055
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.055 1.623 tNET FF 1 IOR11[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR11[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4
5.042 0.000 tSu 1 IOR11[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.623, 87.490%; tC2Q: 0.232, 12.510%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path15

Path Summary:

Slack 1.987
Data Arrival Time 3.055
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.055 1.623 tNET FF 1 IOR11[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR11[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4
5.042 0.000 tSu 1 IOR11[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.623, 87.490%; tC2Q: 0.232, 12.510%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path16

Path Summary:

Slack 1.993
Data Arrival Time 3.049
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
3.049 1.617 tNET FF 1 IOR12[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR12[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4
5.042 0.000 tSu 1 IOR12[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.617, 87.451%; tC2Q: 0.232, 12.549%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path17

Path Summary:

Slack 1.996
Data Arrival Time 3.046
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
3.046 1.614 tNET FF 1 IOL3[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL3[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4
5.042 0.000 tSu 1 IOL3[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.614, 87.429%; tC2Q: 0.232, 12.571%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path18

Path Summary:

Slack 2.074
Data Arrival Time 2.968
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/CLK
1.433 0.232 tC2Q RF 10 R16C25[1][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[0].calib[0]/Q
2.968 1.535 tNET FF 1 IOR9[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOR9[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4
5.042 0.000 tSu 1 IOR9[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.535, 86.872%; tC2Q: 0.232, 13.128%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path19

Path Summary:

Slack 2.285
Data Arrival Time 2.758
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.758 1.325 tNET FF 1 IOL12[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL12[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4
5.042 0.000 tSu 1 IOL12[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.325, 85.101%; tC2Q: 0.232, 14.899%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path20

Path Summary:

Slack 2.285
Data Arrival Time 2.758
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.758 1.325 tNET FF 1 IOL12[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL12[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4
5.042 0.000 tSu 1 IOL12[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.325, 85.101%; tC2Q: 0.232, 14.899%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path21

Path Summary:

Slack 2.325
Data Arrival Time 2.717
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.717 1.285 tNET FF 1 IOL8[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL8[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4
5.042 0.000 tSu 1 IOL8[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.285, 84.705%; tC2Q: 0.232, 15.295%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path22

Path Summary:

Slack 2.325
Data Arrival Time 2.717
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.717 1.285 tNET FF 1 IOL8[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL8[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4
5.042 0.000 tSu 1 IOL8[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.285, 84.705%; tC2Q: 0.232, 15.295%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path23

Path Summary:

Slack 2.334
Data Arrival Time 2.708
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.708 1.276 tNET FF 1 IOL9[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL9[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4
5.042 0.000 tSu 1 IOL9[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.276, 84.613%; tC2Q: 0.232, 15.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path24

Path Summary:

Slack 2.372
Data Arrival Time 2.670
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.670 1.238 tNET FF 1 IOL13[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL13[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4
5.042 0.000 tSu 1 IOL13[B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.238, 84.216%; tC2Q: 0.232, 15.784%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Path25

Path Summary:

Slack 2.533
Data Arrival Time 2.509
Data Required Time 5.042
From u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
Launch Clk clk_x1:[R]
Latch Clk clk_x2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
1.201 1.201 tNET RR 1 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/CLK
1.433 0.232 tC2Q RF 10 R16C25[0][A] u_psram_top/u_psram_top/u_psram_init/read_calibration[1].calib[1]/Q
2.509 1.077 tNET FF 1 IOL15[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x2
5.000 0.000 tCL RR 40 UNPLACED u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT
5.442 0.442 tNET RR 1 IOL15[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4/FCLK
5.042 -0.400 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4
5.042 0.000 tSu 1 IOL15[A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew -0.758
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.077, 82.272%; tC2Q: 0.232, 17.728%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.442, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.194
Data Arrival Time 1.237
Data Required Time 1.043
From u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.104 0.202 tC2Q RR 7 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.237 0.133 tNET RR 1 BSRAM_R46[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/WREA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 BSRAM_R46[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_3/CLKA
0.902 0.000 tUnc u_la0_top/u_ao_mem_ctrl/mem_mem_0_3
1.043 0.141 tHld 1 BSRAM_R46[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path2

Path Summary:

Slack 0.194
Data Arrival Time 1.237
Data Required Time 1.043
From u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_2
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.104 0.202 tC2Q RR 7 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.237 0.133 tNET RR 1 BSRAM_R28[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2/WREA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 BSRAM_R28[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2/CLKA
0.902 0.000 tUnc u_la0_top/u_ao_mem_ctrl/mem_mem_0_2
1.043 0.141 tHld 1 BSRAM_R28[1] u_la0_top/u_ao_mem_ctrl/mem_mem_0_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path3

Path Summary:

Slack 0.194
Data Arrival Time 1.237
Data Required Time 1.043
From u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.104 0.202 tC2Q RR 7 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.237 0.133 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/WREA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA
0.902 0.000 tUnc u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
1.043 0.141 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path4

Path Summary:

Slack 0.194
Data Arrival Time 1.237
Data Required Time 1.043
From u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.104 0.202 tC2Q RR 7 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/Q
1.237 0.133 tNET RR 1 BSRAM_R28[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/WREA

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 BSRAM_R28[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/CLKA
0.902 0.000 tUnc u_la0_top/u_ao_mem_ctrl/mem_mem_0_0
1.043 0.141 tHld 1 BSRAM_R28[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.133, 39.641%; tC2Q: 0.202, 60.359%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path5

Path Summary:

Slack 0.225
Data Arrival Time 1.376
Data Required Time 1.151
From u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R11C10[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]/CLK
1.104 0.202 tC2Q RR 1 R11C10[0][A] u_la0_top/u_ao_mem_ctrl/data_reg_Z[34]/Q
1.376 0.272 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/DI16

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA
0.902 0.000 tUnc u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
1.151 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path6

Path Summary:

Slack 0.307
Data Arrival Time 1.220
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[8]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[9]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[8]/CLK
1.103 0.201 tC2Q RF 1 R20C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[8]/Q
1.220 0.117 tNET FF 1 R20C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[9]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[9]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[9]
0.913 0.011 tHld 1 R20C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[9]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path7

Path Summary:

Slack 0.307
Data Arrival Time 1.220
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[18]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[19]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R25C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[18]/CLK
1.103 0.201 tC2Q RF 1 R25C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[18]/Q
1.220 0.117 tNET FF 1 R25C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[19]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R25C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[19]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[19]
0.913 0.011 tHld 1 R25C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[19]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path8

Path Summary:

Slack 0.307
Data Arrival Time 1.220
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/fixed_32cs.wr_en_delay_all[7]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C39[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/fixed_32cs.wr_en_delay_all[7]/CLK
1.103 0.201 tC2Q RF 1 R18C39[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/fixed_32cs.wr_en_delay_all[7]/Q
1.220 0.117 tNET FF 1 R18C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]
0.913 0.011 tHld 1 R18C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path9

Path Summary:

Slack 0.307
Data Arrival Time 1.220
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[11]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C39[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[11]/CLK
1.103 0.201 tC2Q RF 1 R20C39[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[11]/Q
1.220 0.117 tNET FF 1 R20C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]
0.913 0.011 tHld 1 R20C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path10

Path Summary:

Slack 0.307
Data Arrival Time 1.220
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_Z[2]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_d_Z[2]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C37[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_Z[2]/CLK
1.103 0.201 tC2Q RF 1 R20C37[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_Z[2]/Q
1.220 0.117 tNET FF 1 R20C37[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_d_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C37[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_d_Z[2]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_d_Z[2]
0.913 0.011 tHld 1 R20C37[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/qi0_d_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path11

Path Summary:

Slack 0.307
Data Arrival Time 1.220
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[13]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]/CLK
1.103 0.201 tC2Q RF 1 R20C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[12]/Q
1.220 0.117 tNET FF 1 R20C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[13]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R20C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[13]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[13]
0.913 0.011 tHld 1 R20C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[13]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path12

Path Summary:

Slack 0.310
Data Arrival Time 1.223
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[16]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[17]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R21C39[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[16]/CLK
1.103 0.201 tC2Q RF 2 R21C39[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[16]/Q
1.223 0.120 tNET FF 1 R21C39[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[17]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R21C39[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[17]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[17]
0.913 0.011 tHld 1 R21C39[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[17]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path13

Path Summary:

Slack 0.310
Data Arrival Time 1.223
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[0]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]/CLK
1.103 0.201 tC2Q RF 2 R18C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_dqts_Z[5]/Q
1.223 0.120 tNET FF 1 R18C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[0]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[0]
0.913 0.011 tHld 1 R18C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path14

Path Summary:

Slack 0.310
Data Arrival Time 1.223
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[20]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[21]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R22C39[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[20]/CLK
1.103 0.201 tC2Q RF 2 R22C39[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[20]/Q
1.223 0.120 tNET FF 1 R22C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[21]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R22C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[21]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[21]
0.913 0.011 tHld 1 R22C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r[21]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path15

Path Summary:

Slack 0.310
Data Arrival Time 1.223
Data Required Time 0.913
From u_test/sw_syn_Z[1]
To u_test/sw_syn_Z[2]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R22C30[1][B] u_test/sw_syn_Z[1]/CLK
1.103 0.201 tC2Q RF 2 R22C30[1][B] u_test/sw_syn_Z[1]/Q
1.223 0.120 tNET FF 1 R22C30[0][A] u_test/sw_syn_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R22C30[0][A] u_test/sw_syn_Z[2]/CLK
0.902 0.000 tUnc u_test/sw_syn_Z[2]
0.913 0.011 tHld 1 R22C30[0][A] u_test/sw_syn_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path16

Path Summary:

Slack 0.310
Data Arrival Time 1.223
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[3]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[4]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C40[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[3]/CLK
1.103 0.201 tC2Q RF 2 R18C40[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[3]/Q
1.223 0.120 tNET FF 1 R18C40[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C40[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[4]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[4]
0.913 0.011 tHld 1 R18C40[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[4]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.120, 37.432%; tC2Q: 0.201, 62.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path17

Path Summary:

Slack 0.312
Data Arrival Time 1.225
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[5]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[6]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C40[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[5]/CLK
1.103 0.201 tC2Q RF 1 R18C40[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[5]/Q
1.225 0.122 tNET FF 1 R18C41[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R18C41[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[6]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[6]
0.913 0.011 tHld 1 R18C41[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_r_Z[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path18

Path Summary:

Slack 0.312
Data Arrival Time 1.225
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[49]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/q9_Z[2]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R25C40[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[49]/CLK
1.103 0.201 tC2Q RF 1 R25C40[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[49]/Q
1.225 0.122 tNET FF 1 R25C40[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/q9_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R25C40[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/q9_Z[2]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/q9_Z[2]
0.913 0.011 tHld 1 R25C40[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/q9_Z[2]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path19

Path Summary:

Slack 0.314
Data Arrival Time 1.227
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[6]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R16C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]/CLK
1.103 0.201 tC2Q RF 2 R16C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]/Q
1.227 0.124 tNET FF 1 R16C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R16C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[6]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[6]
0.913 0.011 tHld 1 R16C39[2][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 38.091%; tC2Q: 0.201, 61.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path20

Path Summary:

Slack 0.314
Data Arrival Time 1.227
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[4]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R16C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[4]/CLK
1.103 0.201 tC2Q RF 2 R16C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[4]/Q
1.227 0.124 tNET FF 1 R16C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R16C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]
0.913 0.011 tHld 1 R16C39[0][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/cats_Z[5]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 38.091%; tC2Q: 0.201, 61.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path21

Path Summary:

Slack 0.314
Data Arrival Time 1.227
Data Required Time 0.913
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[5]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[6]
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R17C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[5]/CLK
1.103 0.201 tC2Q RF 2 R17C39[2][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[5]/Q
1.227 0.124 tNET FF 1 R17C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R17C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[6]/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[6]
0.913 0.011 tHld 1 R17C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.rd_datats[6]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.124, 38.091%; tC2Q: 0.201, 61.909%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path22

Path Summary:

Slack 0.327
Data Arrival Time 1.241
Data Required Time 0.914
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[2]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R25C35[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[2]/CLK
1.103 0.201 tC2Q RF 13 R25C35[1][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[2]/Q
1.241 0.138 tNET FF 1 R24C35 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1/WAD2

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R24C35 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1
0.914 0.012 tHld 1 R24C35 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.138, 40.758%; tC2Q: 0.201, 59.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path23

Path Summary:

Slack 0.327
Data Arrival Time 1.241
Data Required Time 0.914
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.wr_ptr[1]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_mask.mem_mask_mem_mask_0_2
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R22C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.wr_ptr[1]/CLK
1.103 0.201 tC2Q RF 11 R22C39[0][B] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.wr_ptr[1]/Q
1.241 0.138 tNET FF 1 R23C39 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_mask.mem_mask_mem_mask_0_2/WAD1

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R23C39 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_mask.mem_mask_mem_mask_0_2/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_mask.mem_mask_mem_mask_0_2
0.914 0.012 tHld 1 R23C39 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/mem_mask.mem_mask_mem_mask_0_2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.138, 40.758%; tC2Q: 0.201, 59.242%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path24

Path Summary:

Slack 0.330
Data Arrival Time 1.244
Data Required Time 0.914
From u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[0]
To u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R25C35[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[0]/CLK
1.103 0.201 tC2Q RF 12 R25C35[1][A] u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/burst32.wr_ptr[0]/Q
1.244 0.141 tNET FF 1 R24C35 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1/WAD0

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R24C35 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1/CLK
0.902 0.000 tUnc u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1
0.914 0.012 tHld 1 R24C35 u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[1].u_psram_lane/mem_mask.mem_mask_mem_mask_0_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.141, 41.164%; tC2Q: 0.201, 58.836%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path25

Path Summary:

Slack 0.335
Data Arrival Time 1.486
Data Required Time 1.151
From u_la0_top/u_ao_mem_ctrl/data_reg_Z[33]
To u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R12C9[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_Z[33]/CLK
1.104 0.202 tC2Q RR 1 R12C9[2][B] u_la0_top/u_ao_mem_ctrl/data_reg_Z[33]/Q
1.486 0.382 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/DI15

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA
0.902 0.000 tUnc u_la0_top/u_ao_mem_ctrl/mem_mem_0_1
1.151 0.249 tHld 1 BSRAM_R10[0] u_la0_top/u_ao_mem_ctrl/mem_mem_0_1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 3.447
Data Arrival Time 7.519
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.519 1.058 tNET FF 1 R5C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R5C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]
10.966 -0.035 tSu 1 R5C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.058, 82.020%; tC2Q: 0.232, 17.980%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path2

Path Summary:

Slack 3.447
Data Arrival Time 7.519
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.519 1.058 tNET FF 1 R5C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R5C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]
10.966 -0.035 tSu 1 R5C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.058, 82.020%; tC2Q: 0.232, 17.980%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path3

Path Summary:

Slack 3.654
Data Arrival Time 7.311
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/triger_level_cnt_Z[2]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.311 0.851 tNET FF 1 R4C4[2][A] u_la0_top/triger_level_cnt_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C4[2][A] u_la0_top/triger_level_cnt_Z[2]/CLK
11.001 -0.200 tUnc u_la0_top/triger_level_cnt_Z[2]
10.966 -0.035 tSu 1 R4C4[2][A] u_la0_top/triger_level_cnt_Z[2]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.851, 78.576%; tC2Q: 0.232, 21.424%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path4

Path Summary:

Slack 3.654
Data Arrival Time 7.311
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/triger_level_cnt_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.311 0.851 tNET FF 1 R4C4[1][A] u_la0_top/triger_level_cnt_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C4[1][A] u_la0_top/triger_level_cnt_Z[0]/CLK
11.001 -0.200 tUnc u_la0_top/triger_level_cnt_Z[0]
10.966 -0.035 tSu 1 R4C4[1][A] u_la0_top/triger_level_cnt_Z[0]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.851, 78.576%; tC2Q: 0.232, 21.424%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path5

Path Summary:

Slack 3.654
Data Arrival Time 7.311
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/triger_level_cnt_Z[3]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.311 0.851 tNET FF 1 R4C4[2][B] u_la0_top/triger_level_cnt_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C4[2][B] u_la0_top/triger_level_cnt_Z[3]/CLK
11.001 -0.200 tUnc u_la0_top/triger_level_cnt_Z[3]
10.966 -0.035 tSu 1 R4C4[2][B] u_la0_top/triger_level_cnt_Z[3]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.851, 78.576%; tC2Q: 0.232, 21.424%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path6

Path Summary:

Slack 3.654
Data Arrival Time 7.311
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/triger_level_cnt_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.311 0.851 tNET FF 1 R4C4[1][B] u_la0_top/triger_level_cnt_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C4[1][B] u_la0_top/triger_level_cnt_Z[1]/CLK
11.001 -0.200 tUnc u_la0_top/triger_level_cnt_Z[1]
10.966 -0.035 tSu 1 R4C4[1][B] u_la0_top/triger_level_cnt_Z[1]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.851, 78.576%; tC2Q: 0.232, 21.424%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path7

Path Summary:

Slack 3.660
Data Arrival Time 7.306
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.306 0.845 tNET FF 1 R2C7[1][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R2C7[1][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z
10.966 -0.035 tSu 1 R2C7[1][A] u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 78.462%; tC2Q: 0.232, 21.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path8

Path Summary:

Slack 3.660
Data Arrival Time 7.306
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.306 0.845 tNET FF 1 R2C7[2][B] u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R2C7[2][B] u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]/CLK
11.001 -0.200 tUnc u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]
10.966 -0.035 tSu 1 R2C7[2][B] u_la0_top/genblk1.u_ao_match_0/trig_dly_Z[0]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 78.462%; tC2Q: 0.232, 21.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path9

Path Summary:

Slack 3.660
Data Arrival Time 7.306
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.306 0.845 tNET FF 1 R2C7[2][A] u_la0_top/capture_window_sel_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R2C7[2][A] u_la0_top/capture_window_sel_Z[0]/CLK
11.001 -0.200 tUnc u_la0_top/capture_window_sel_Z[0]
10.966 -0.035 tSu 1 R2C7[2][A] u_la0_top/capture_window_sel_Z[0]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 78.462%; tC2Q: 0.232, 21.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path10

Path Summary:

Slack 3.660
Data Arrival Time 7.306
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel[3]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.306 0.845 tNET FF 1 R2C7[0][A] u_la0_top/capture_window_sel[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R2C7[0][A] u_la0_top/capture_window_sel[3]/CLK
11.001 -0.200 tUnc u_la0_top/capture_window_sel[3]
10.966 -0.035 tSu 1 R2C7[0][A] u_la0_top/capture_window_sel[3]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 78.462%; tC2Q: 0.232, 21.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path11

Path Summary:

Slack 3.660
Data Arrival Time 7.306
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_dly_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.306 0.845 tNET FF 1 R2C7[0][B] u_la0_top/internal_reg_start_dly_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R2C7[0][B] u_la0_top/internal_reg_start_dly_Z[0]/CLK
11.001 -0.200 tUnc u_la0_top/internal_reg_start_dly_Z[0]
10.966 -0.035 tSu 1 R2C7[0][B] u_la0_top/internal_reg_start_dly_Z[0]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.845, 78.462%; tC2Q: 0.232, 21.538%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path12

Path Summary:

Slack 3.666
Data Arrival Time 7.300
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.300 0.839 tNET FF 1 R3C5[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C5[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]
10.966 -0.035 tSu 1 R3C5[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.839, 78.347%; tC2Q: 0.232, 21.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path13

Path Summary:

Slack 3.666
Data Arrival Time 7.300
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.300 0.839 tNET FF 1 R3C5[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C5[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]
10.966 -0.035 tSu 1 R3C5[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.839, 78.347%; tC2Q: 0.232, 21.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path14

Path Summary:

Slack 3.666
Data Arrival Time 7.300
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.300 0.839 tNET FF 1 R3C5[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C5[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]
10.966 -0.035 tSu 1 R3C5[0][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.839, 78.347%; tC2Q: 0.232, 21.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path15

Path Summary:

Slack 3.666
Data Arrival Time 7.300
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.300 0.839 tNET FF 1 R3C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
10.966 -0.035 tSu 1 R3C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.839, 78.347%; tC2Q: 0.232, 21.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path16

Path Summary:

Slack 3.666
Data Arrival Time 7.300
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.300 0.839 tNET FF 1 R3C5[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C5[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]
10.966 -0.035 tSu 1 R3C5[1][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.839, 78.347%; tC2Q: 0.232, 21.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path17

Path Summary:

Slack 3.666
Data Arrival Time 7.300
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.300 0.839 tNET FF 1 R3C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
10.966 -0.035 tSu 1 R3C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.839, 78.347%; tC2Q: 0.232, 21.653%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path18

Path Summary:

Slack 3.677
Data Arrival Time 7.288
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.288 0.828 tNET FF 1 R3C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
10.966 -0.035 tSu 1 R3C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.828, 78.113%; tC2Q: 0.232, 21.887%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path19

Path Summary:

Slack 3.677
Data Arrival Time 7.288
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.288 0.828 tNET FF 1 R3C4[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C4[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
10.966 -0.035 tSu 1 R3C4[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.828, 78.113%; tC2Q: 0.232, 21.887%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path20

Path Summary:

Slack 3.683
Data Arrival Time 7.282
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/genblk1.u_ao_match_0/match_sep
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.282 0.822 tNET FF 1 R9C2[1][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R9C2[1][B] u_la0_top/genblk1.u_ao_match_0/match_sep/CLK
11.001 -0.200 tUnc u_la0_top/genblk1.u_ao_match_0/match_sep
10.966 -0.035 tSu 1 R9C2[1][B] u_la0_top/genblk1.u_ao_match_0/match_sep

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.822, 77.986%; tC2Q: 0.232, 22.014%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path21

Path Summary:

Slack 3.690
Data Arrival Time 7.276
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.276 0.816 tNET FF 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
10.966 -0.035 tSu 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.816, 77.855%; tC2Q: 0.232, 22.145%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path22

Path Summary:

Slack 3.690
Data Arrival Time 7.276
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.276 0.816 tNET FF 1 R4C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
10.966 -0.035 tSu 1 R4C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.816, 77.855%; tC2Q: 0.232, 22.145%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path23

Path Summary:

Slack 3.695
Data Arrival Time 7.270
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.270 0.810 tNET FF 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
10.966 -0.035 tSu 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.810, 77.733%; tC2Q: 0.232, 22.267%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path24

Path Summary:

Slack 3.861
Data Arrival Time 7.104
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.104 0.644 tNET FF 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
10.966 -0.035 tSu 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.644, 73.511%; tC2Q: 0.232, 26.489%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Path25

Path Summary:

Slack 3.903
Data Arrival Time 7.063
Data Required Time 10.966
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.460 0.232 tC2Q FF 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
7.063 0.602 tNET FF 1 R4C3[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
10.000 10.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
11.201 1.201 tNET RR 1 R4C3[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
11.001 -0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
10.966 -0.035 tSu 1 R4C3[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew -0.028
Setup Relationship 5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.228, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.602, 72.197%; tC2Q: 0.232, 27.803%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.201, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 5.385
Data Arrival Time 6.498
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.498 0.383 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z
1.113 0.011 tHld 1 R2C6[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.383, 65.457%; tC2Q: 0.202, 34.543%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path2

Path Summary:

Slack 5.399
Data Arrival Time 6.512
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/trigger_seq_start_Z
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.512 0.397 tNET RR 1 R2C3[1][A] u_la0_top/trigger_seq_start_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C3[1][A] u_la0_top/trigger_seq_start_Z/CLK
1.102 0.200 tUnc u_la0_top/trigger_seq_start_Z
1.113 0.011 tHld 1 R2C3[1][A] u_la0_top/trigger_seq_start_Z

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.397, 66.259%; tC2Q: 0.202, 33.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path3

Path Summary:

Slack 5.399
Data Arrival Time 6.512
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_force_triger_syn_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.512 0.397 tNET RR 1 R2C3[2][B] u_la0_top/internal_reg_force_triger_syn_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C3[2][B] u_la0_top/internal_reg_force_triger_syn_Z[0]/CLK
1.102 0.200 tUnc u_la0_top/internal_reg_force_triger_syn_Z[0]
1.113 0.011 tHld 1 R2C3[2][B] u_la0_top/internal_reg_force_triger_syn_Z[0]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.397, 66.259%; tC2Q: 0.202, 33.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path4

Path Summary:

Slack 5.399
Data Arrival Time 6.512
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_dly_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.512 0.397 tNET RR 1 R2C3[0][A] u_la0_top/internal_reg_start_dly_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C3[0][A] u_la0_top/internal_reg_start_dly_Z[1]/CLK
1.102 0.200 tUnc u_la0_top/internal_reg_start_dly_Z[1]
1.113 0.011 tHld 1 R2C3[0][A] u_la0_top/internal_reg_start_dly_Z[1]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.397, 66.259%; tC2Q: 0.202, 33.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path5

Path Summary:

Slack 5.399
Data Arrival Time 6.512
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_force_triger_syn_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.512 0.397 tNET RR 1 R2C3[2][A] u_la0_top/internal_reg_force_triger_syn_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C3[2][A] u_la0_top/internal_reg_force_triger_syn_Z[1]/CLK
1.102 0.200 tUnc u_la0_top/internal_reg_force_triger_syn_Z[1]
1.113 0.011 tHld 1 R2C3[2][A] u_la0_top/internal_reg_force_triger_syn_Z[1]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.397, 66.259%; tC2Q: 0.202, 33.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path6

Path Summary:

Slack 5.399
Data Arrival Time 6.512
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/capture_end_dly_Z
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.512 0.397 tNET RR 1 R2C3[0][B] u_la0_top/capture_end_dly_Z/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C3[0][B] u_la0_top/capture_end_dly_Z/CLK
1.102 0.200 tUnc u_la0_top/capture_end_dly_Z
1.113 0.011 tHld 1 R2C3[0][B] u_la0_top/capture_end_dly_Z

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.397, 66.259%; tC2Q: 0.202, 33.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path7

Path Summary:

Slack 5.405
Data Arrival Time 6.518
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_loop_Z
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.518 0.403 tNET RR 1 R2C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_loop_Z
1.113 0.011 tHld 1 R2C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_loop_Z

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.403, 66.627%; tC2Q: 0.202, 33.373%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path8

Path Summary:

Slack 5.408
Data Arrival Time 6.521
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.521 0.406 tNET RR 1 R2C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]
1.113 0.011 tHld 1 R2C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 66.791%; tC2Q: 0.202, 33.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path9

Path Summary:

Slack 5.408
Data Arrival Time 6.521
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.521 0.406 tNET RR 1 R2C4[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C4[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]
1.113 0.011 tHld 1 R2C4[1][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 66.791%; tC2Q: 0.202, 33.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path10

Path Summary:

Slack 5.408
Data Arrival Time 6.521
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.521 0.406 tNET RR 1 R2C4[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C4[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]
1.113 0.011 tHld 1 R2C4[0][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 66.791%; tC2Q: 0.202, 33.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path11

Path Summary:

Slack 5.408
Data Arrival Time 6.521
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.521 0.406 tNET RR 1 R2C4[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C4[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]
1.113 0.011 tHld 1 R2C4[1][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 66.791%; tC2Q: 0.202, 33.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path12

Path Summary:

Slack 5.408
Data Arrival Time 6.521
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.521 0.406 tNET RR 1 R2C4[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C4[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]
1.113 0.011 tHld 1 R2C4[0][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 66.791%; tC2Q: 0.202, 33.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path13

Path Summary:

Slack 5.408
Data Arrival Time 6.521
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_syn_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.521 0.406 tNET RR 1 R2C4[2][B] u_la0_top/internal_reg_start_syn_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R2C4[2][B] u_la0_top/internal_reg_start_syn_Z[1]/CLK
1.102 0.200 tUnc u_la0_top/internal_reg_start_syn_Z[1]
1.113 0.011 tHld 1 R2C4[2][B] u_la0_top/internal_reg_start_syn_Z[1]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.406, 66.791%; tC2Q: 0.202, 33.209%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path14

Path Summary:

Slack 5.411
Data Arrival Time 6.524
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.524 0.409 tNET RR 1 R4C3[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C3[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]
1.113 0.011 tHld 1 R4C3[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 66.954%; tC2Q: 0.202, 33.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path15

Path Summary:

Slack 5.411
Data Arrival Time 6.524
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/internal_reg_start_syn_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.524 0.409 tNET RR 1 R4C3[1][A] u_la0_top/internal_reg_start_syn_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C3[1][A] u_la0_top/internal_reg_start_syn_Z[0]/CLK
1.102 0.200 tUnc u_la0_top/internal_reg_start_syn_Z[0]
1.113 0.011 tHld 1 R4C3[1][A] u_la0_top/internal_reg_start_syn_Z[0]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 66.954%; tC2Q: 0.202, 33.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path16

Path Summary:

Slack 5.411
Data Arrival Time 6.524
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.524 0.409 tNET RR 1 R4C3[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C3[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]
1.113 0.011 tHld 1 R4C3[0][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 66.954%; tC2Q: 0.202, 33.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path17

Path Summary:

Slack 5.411
Data Arrival Time 6.524
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.524 0.409 tNET RR 1 R4C3[1][B] u_la0_top/capture_window_sel_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C3[1][B] u_la0_top/capture_window_sel_Z[1]/CLK
1.102 0.200 tUnc u_la0_top/capture_window_sel_Z[1]
1.113 0.011 tHld 1 R4C3[1][B] u_la0_top/capture_window_sel_Z[1]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 66.954%; tC2Q: 0.202, 33.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path18

Path Summary:

Slack 5.411
Data Arrival Time 6.524
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/capture_window_sel_Z[2]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.524 0.409 tNET RR 1 R4C3[2][A] u_la0_top/capture_window_sel_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C3[2][A] u_la0_top/capture_window_sel_Z[2]/CLK
1.102 0.200 tUnc u_la0_top/capture_window_sel_Z[2]
1.113 0.011 tHld 1 R4C3[2][A] u_la0_top/capture_window_sel_Z[2]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.409, 66.954%; tC2Q: 0.202, 33.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path19

Path Summary:

Slack 5.522
Data Arrival Time 6.635
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.635 0.520 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]
1.113 0.011 tHld 1 R3C2[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.520, 72.020%; tC2Q: 0.202, 27.980%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path20

Path Summary:

Slack 5.524
Data Arrival Time 6.637
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.637 0.522 tNET RR 1 R3C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R3C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]
1.113 0.011 tHld 1 R3C4[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.522, 72.110%; tC2Q: 0.202, 27.890%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path21

Path Summary:

Slack 5.524
Data Arrival Time 6.637
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.637 0.522 tNET RR 1 R3C4[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R3C4[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]
1.113 0.011 tHld 1 R3C4[2][B] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.522, 72.110%; tC2Q: 0.202, 27.890%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path22

Path Summary:

Slack 5.525
Data Arrival Time 6.638
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.638 0.523 tNET RR 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]
1.113 0.011 tHld 1 R4C2[2][B] u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.523, 72.136%; tC2Q: 0.202, 27.864%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path23

Path Summary:

Slack 5.525
Data Arrival Time 6.638
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.638 0.523 tNET RR 1 R4C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R4C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]
1.113 0.011 tHld 1 R4C2[2][A] u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.523, 72.136%; tC2Q: 0.202, 27.864%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path24

Path Summary:

Slack 5.530
Data Arrival Time 6.643
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.643 0.528 tNET RR 1 R3C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R3C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]
1.113 0.011 tHld 1 R3C5[1][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.528, 72.339%; tC2Q: 0.202, 27.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Path25

Path Summary:

Slack 5.530
Data Arrival Time 6.643
Data Required Time 1.113
From u_la0_top/rst_ao_Z
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
Launch Clk clk_x1:[F]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
5.000 5.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
5.913 0.913 tNET FF 1 R2C2[0][A] u_la0_top/rst_ao_Z/CLK
6.115 0.202 tC2Q FR 44 R2C2[0][A] u_la0_top/rst_ao_Z/Q
6.643 0.528 tNET RR 1 R3C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 911 RIGHTSIDE[0] u_psram_top/u_psram_top/clkdiv/CLKOUT
0.902 0.902 tNET RR 1 R3C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK
1.102 0.200 tUnc u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]
1.113 0.011 tHld 1 R3C5[2][A] u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]

Path Statistics:

Clock Skew -0.011
Hold Relationship -5.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.913, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.528, 72.339%; tC2Q: 0.202, 27.661%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.902, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/rd_data_d_Z[54]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/rd_data_d_Z[54]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/rd_data_d_Z[54]/CLK

MPW2

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/rd_data_d_Z[56]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/rd_data_d_Z[56]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/rd_data_d_Z[56]/CLK

MPW3

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/rd_data_d_Z[60]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/rd_data_d_Z[60]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/rd_data_d_Z[60]/CLK

MPW4

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/rd_data_d_Z[43]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/rd_data_d_Z[43]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/rd_data_d_Z[43]/CLK

MPW5

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/rd_data_d_Z[29]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/rd_data_d_Z[29]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/rd_data_d_Z[29]/CLK

MPW6

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/rd_data_d_Z[7]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/rd_data_d_Z[7]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/rd_data_d_Z[7]/CLK

MPW7

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[42]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[42]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/CA_Z[42]/CLK

MPW8

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.data_mask_d[21]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.data_mask_d[21]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/burst32.data_mask_d[21]/CLK

MPW9

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[6]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[6]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[6]/CLK

MPW10

MPW Summary:

Slack: 3.674
Actual Width: 4.674
Required Width: 1.000
Type: Low Pulse Width
Clock: clk_x1
Objects: u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[5]

Late clock Path:

AT DELAY TYPE RF NODE
5.000 0.000 active clock edge time
5.000 0.000 clk_x1
5.000 0.000 tCL FF u_psram_top/u_psram_top/clkdiv/CLKOUT
6.228 1.228 tNET FF u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[5]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL RR u_psram_top/u_psram_top/clkdiv/CLKOUT
10.902 0.902 tNET RR u_psram_top/u_psram_top/u_psram_init/read_calibration[0].check_cnt[5]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
911 clk_x1 1.712 1.228
96 rd_data_valid_d0 6.169 1.799
79 rd_data_ctrl 5.594 1.653
73 init_calib_c 4.586 2.069
72 data_mask_d_rst 4.474 1.542
67 wr_en_delay_reg 4.795 1.613
67 u_psram_wd.init_done_i_1 3.260 1.347
48 init_calib_rep2 5.967 1.890
47 init_calib_rep1 6.367 2.057
40 clk_x2p 1.539 0.673

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R10C30 0.556
R27C19 0.556
R27C26 0.556
R18C39 0.556
R11C29 0.528
R11C30 0.514
R26C30 0.514
R27C24 0.500
R21C39 0.500
R16C30 0.486

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_x1 -period 10 -waveform {0 5} [get_nets {clk_x1}]
TC_CLOCK Actived create_clock -name clk_x2 -period 5 -waveform {0 2.5} [get_pins {u_psram_top/u_psram_top/u_dqce_clk_x2p/CLKOUT}]