Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu.v C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\gowin_empu_gw1ns4\data\gowin_empu_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.01 |
| Part Number | GW1NS-LV4CQN48C7/I6 |
| Device | GW1NS-4C |
| Created Time | Mon Nov 01 11:12:15 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_EMPU_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.331s, Peak memory usage = 48.566MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 48.566MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 48.566MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 48.566MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 48.566MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 48.566MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 48.566MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 48.566MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 48.566MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 48.566MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 48.566MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 48.566MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.867MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 60.867MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 60.867MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 60.867MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 113 |
| I/O Buf | 113 |
| IBUF | 39 |
| OBUF | 56 |
| IOBUF | 18 |
| Register | 296 |
| DFF | 1 |
| DFFE | 1 |
| DFFP | 7 |
| DFFPE | 26 |
| DFFC | 94 |
| DFFCE | 151 |
| DFFNCE | 16 |
| LUT | 474 |
| LUT2 | 47 |
| LUT3 | 179 |
| LUT4 | 248 |
| INV | 23 |
| INV | 23 |
| BSRAM | 8 |
| SDPB | 8 |
| Black Box | 1 |
| EMCU | 1 |
| User Flash | 1 |
| FLASH256K | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 497(497 LUTs, 0 ALUs) / 4608 | 11% |
| Register | 296 / 3570 | 8% |
| --Register as Latch | 0 / 3570 | 0% |
| --Register as FF | 296 / 3570 | 8% |
| BSRAM | 8 / 10 | 80% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| sys_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | sys_clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | sys_clk | 50.0(MHz) | 90.4(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.466 |
| Data Arrival Time | 6.322 |
| Data Required Time | 10.789 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| Launch Clk | sys_clk[F] |
| Latch Clk | sys_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 312 | sys_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK |
| 1.336 | 0.340 | tC2Q | RF | 8 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q |
| 1.692 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s20/I1 |
| 2.506 | 0.814 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s20/F |
| 2.862 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/I1 |
| 3.676 | 0.814 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/F |
| 4.032 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/I0 |
| 4.797 | 0.765 | tINS | FF | 4 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_5_s5/F |
| 5.152 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/I1 |
| 5.967 | 0.814 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n537_s12/F |
| 6.322 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk | |||
| 10.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 312 | sys_clk_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
| 10.789 | -0.296 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| Clock Skew: | 0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 3.208, 60.231%; route: 1.778, 33.392%; tC2Q: 0.340, 6.377% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:| Slack | 4.672 |
| Data Arrival Time | 6.117 |
| Data Required Time | 10.789 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
| Launch Clk | sys_clk[F] |
| Latch Clk | sys_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 312 | sys_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK |
| 1.336 | 0.340 | tC2Q | RF | 8 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q |
| 1.692 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s20/I1 |
| 2.506 | 0.814 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s20/F |
| 2.862 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/I1 |
| 3.676 | 0.814 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/F |
| 4.032 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s15/I0 |
| 4.797 | 0.765 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s15/F |
| 5.152 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/I2 |
| 5.761 | 0.609 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s12/F |
| 6.117 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk | |||
| 10.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 312 | sys_clk_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3/CLK |
| 10.789 | -0.296 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_0_s3 |
| Clock Skew: | 0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 3.003, 58.636%; route: 1.778, 34.731%; tC2Q: 0.340, 6.633% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 3
Path Summary:| Slack | 4.817 |
| Data Arrival Time | 5.972 |
| Data Required Time | 10.789 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
| Launch Clk | sys_clk[F] |
| Latch Clk | sys_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 312 | sys_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/CLK |
| 1.336 | 0.340 | tC2Q | RF | 8 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/data_cnt_1_s1/Q |
| 1.692 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s20/I1 |
| 2.506 | 0.814 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s20/F |
| 2.862 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/I1 |
| 3.676 | 0.814 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s18/F |
| 4.032 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s15/I0 |
| 4.797 | 0.765 | tINS | FF | 2 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n539_s15/F |
| 5.152 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/I3 |
| 5.616 | 0.464 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n538_s13/F |
| 5.972 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk | |||
| 10.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 312 | sys_clk_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3/CLK |
| 10.789 | -0.296 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_1_s3 |
| Clock Skew: | 0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 2.857, 57.430%; route: 1.778, 35.744%; tC2Q: 0.340, 6.826% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 4
Path Summary:| Slack | 5.820 |
| Data Arrival Time | 14.880 |
| Data Required Time | 20.700 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1 |
| Launch Clk | sys_clk[R] |
| Latch Clk | sys_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk | |||
| 10.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 312 | sys_clk_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
| 11.425 | 0.340 | tC2Q | FF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/Q |
| 11.780 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/I1 |
| 12.595 | 0.814 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/F |
| 12.950 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/I2 |
| 13.560 | 0.609 | tINS | FF | 10 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/F |
| 13.915 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n716_s0/I2 |
| 14.524 | 0.609 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n716_s0/F |
| 14.880 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 312 | sys_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_0_s1 |
| Clock Skew: | -0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
| Arrival Data Path Delay: | cell: 2.033, 53.561%; route: 1.423, 37.490%; tC2Q: 0.340, 8.949% |
| Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
Path 5
Path Summary:| Slack | 5.965 |
| Data Arrival Time | 14.735 |
| Data Required Time | 20.700 |
| From | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3 |
| To | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1 |
| Launch Clk | sys_clk[R] |
| Latch Clk | sys_clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk | |||
| 10.000 | 0.000 | tCL | FF | 1 | sys_clk_ibuf/I |
| 10.729 | 0.729 | tINS | FF | 312 | sys_clk_ibuf/O |
| 11.085 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/CLK |
| 11.425 | 0.340 | tC2Q | FF | 5 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n_status_2_s3/Q |
| 11.780 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/I1 |
| 12.595 | 0.814 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s1/F |
| 12.950 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/I2 |
| 13.560 | 0.609 | tINS | FF | 10 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n671_s0/F |
| 13.915 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n709_s0/I3 |
| 14.379 | 0.464 | tINS | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/n709_s0/F |
| 14.735 | 0.356 | tNET | FF | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | sys_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | sys_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 312 | sys_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1/CLK |
| 20.700 | -0.296 | tSu | 1 | Gowin_EMPU_inst/u_gw_peripherals_interconnect/u_gw_cmsdk_apb2_spi/tx_shift_data_7_s1 |
| Clock Skew: | -0.089 |
| Setup Relationship: | 10.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |
| Arrival Data Path Delay: | cell: 1.887, 51.712%; route: 1.423, 38.982%; tC2Q: 0.340, 9.306% |
| Required Clock Path Delay: | cell: 0.729, 67.222%; route: 0.356, 32.778% |