@W: MT246 :"e:\ip_refdesign\gowin_i3c_ddr_extension_refdesign\write\project_m\src\gw_pll\gw_pll.v":26:4:26:11|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GW_PLL|clkout_inferred_clock with period 25.70ns. Please declare a user-defined clock on net j8_4_c.
@W: MT420 |Found inferred clock SclkGen|scl_i_i_1z_inferred_clock with period 23.34ns. Please declare a user-defined clock on net iPhy.iPhy.scl_i_i.
