@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":17:7:17:11|Removing wire led_4, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":18:7:18:11|Removing wire led_5, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":19:7:19:11|Removing wire led_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":49:7:49:11|Removing wire j8_31, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":50:7:50:11|Removing wire j8_32, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":51:7:51:11|Removing wire j8_33, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":52:7:52:11|Removing wire j8_34, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":53:7:53:11|Removing wire j8_35, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":54:7:54:11|Removing wire j8_36, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":55:7:55:11|Removing wire j8_37, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":56:7:56:11|Removing wire j8_38, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":60:7:60:10|Removing wire j9_5, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":61:7:61:10|Removing wire j9_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":62:7:62:10|Removing wire j9_7, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":63:7:63:10|Removing wire j9_8, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":64:7:64:10|Removing wire j9_9, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":65:7:65:11|Removing wire j9_10, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":66:7:66:11|Removing wire j9_11, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":67:7:67:11|Removing wire j9_12, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":68:7:68:11|Removing wire j9_13, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":69:7:69:11|Removing wire j9_14, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":70:7:70:11|Removing wire j9_15, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":71:7:71:11|Removing wire j9_16, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":72:7:72:11|Removing wire j9_17, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":73:7:73:11|Removing wire j9_18, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":74:7:74:11|Removing wire j9_19, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":75:7:75:11|Removing wire j9_20, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":76:7:76:11|Removing wire j9_21, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":77:7:77:11|Removing wire j9_22, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":78:7:78:11|Removing wire j9_23, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":79:7:79:11|Removing wire j9_24, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":80:7:80:11|Removing wire j9_25, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":81:7:81:11|Removing wire j9_26, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":82:7:82:11|Removing wire j9_27, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":83:7:83:11|Removing wire j9_28, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":84:7:84:11|Removing wire j9_29, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":85:7:85:11|Removing wire j9_30, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":86:7:86:11|Removing wire j9_31, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":87:7:87:11|Removing wire j9_32, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":88:7:88:11|Removing wire j9_33, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":89:7:89:11|Removing wire j9_34, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":90:7:90:11|Removing wire j9_35, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":91:7:91:11|Removing wire j9_36, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":92:7:92:11|Removing wire j9_37, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":93:7:93:11|Removing wire j9_38, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":98:8:98:12|Removing wire j10_6, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":99:8:99:12|Removing wire j10_9, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":100:8:100:13|Removing wire j10_10, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":205:18:205:21|Removing wire key3, as there is no assignment to it.
@W: CG360 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":205:23:205:26|Removing wire key4, as there is no assignment to it.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":17:7:17:11|*Output led_4 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":18:7:18:11|*Output led_5 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":19:7:19:11|*Output led_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":49:7:49:11|*Output j8_31 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":50:7:50:11|*Output j8_32 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":51:7:51:11|*Output j8_33 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":52:7:52:11|*Output j8_34 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":53:7:53:11|*Output j8_35 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":54:7:54:11|*Output j8_36 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":55:7:55:11|*Output j8_37 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":56:7:56:11|*Output j8_38 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":60:7:60:10|*Output j9_5 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":61:7:61:10|*Output j9_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":62:7:62:10|*Output j9_7 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":63:7:63:10|*Output j9_8 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":64:7:64:10|*Output j9_9 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":65:7:65:11|*Output j9_10 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":66:7:66:11|*Output j9_11 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":67:7:67:11|*Output j9_12 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":68:7:68:11|*Output j9_13 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":69:7:69:11|*Output j9_14 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":70:7:70:11|*Output j9_15 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":71:7:71:11|*Output j9_16 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":72:7:72:11|*Output j9_17 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":73:7:73:11|*Output j9_18 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":74:7:74:11|*Output j9_19 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":75:7:75:11|*Output j9_20 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":76:7:76:11|*Output j9_21 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":77:7:77:11|*Output j9_22 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":78:7:78:11|*Output j9_23 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":79:7:79:11|*Output j9_24 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":80:7:80:11|*Output j9_25 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":81:7:81:11|*Output j9_26 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":82:7:82:11|*Output j9_27 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":83:7:83:11|*Output j9_28 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":84:7:84:11|*Output j9_29 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":85:7:85:11|*Output j9_30 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":86:7:86:11|*Output j9_31 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":87:7:87:11|*Output j9_32 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":88:7:88:11|*Output j9_33 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":89:7:89:11|*Output j9_34 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":90:7:90:11|*Output j9_35 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":91:7:91:11|*Output j9_36 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":92:7:92:11|*Output j9_37 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":93:7:93:11|*Output j9_38 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":98:8:98:12|*Output j10_6 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":99:8:99:12|*Output j10_9 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":100:8:100:13|*Output j10_10 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"E:\IP_refdesign\Gowin_I3C_DDR_eXtension_refDesign\write\Project_M\src\master.sv":314:0:314:5|Pruning unused register pcInc. Make sure that there are no unused intermediate registers.

