#Build: Synplify Pro (R) O-2018.09G-SP1-1-Beta1, Build 141R, Mar 12 2019 #install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro #OS: Windows 7 6.1 #Hostname: Desktop-2019KKU # Tue Sep 17 10:32:55 2019 #Implementation: rev_1 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\generic\gw1n.v" (library work) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\gw_i2c_slave\src\i2c_slave_defines.v" (library work) @I::"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v" (library work) @I::"D:\gw_i2c_slave\src\rom_init.v" (library work) @I::"D:\gw_i2c_slave\src\gw_i2c_slave.v" (library work) @I::"D:\gw_i2c_slave\src\gowin_pll\gowin_pll.v" (library work) Verilog syntax check successful! Options changed - recompiling Selecting top level module gw_i2c_slave @N:CG364 : gw1n.v(1488) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : gowin_pll.v(8) | Synthesizing module Gowin_PLL in library work. Running optimization stage 1 on Gowin_PLL ....... @N:CG364 : I2C_SLAVE_TOP.v(105) | Synthesizing module i2c_slave in library work. @N:CG179 : I2C_SLAVE_TOP.v(294) | Removing redundant assignment. Running optimization stage 1 on i2c_slave ....... @W:CL169 : I2C_SLAVE_TOP.v(362) | Pruning unused register is_continue. Make sure that there are no unused intermediate registers. @W:CL271 : I2C_SLAVE_TOP.v(362) | Pruning unused bits 7 to 0 of data_len_reg[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @A:CL291 : I2C_SLAVE_TOP.v(362) | Register nstate with asynchronous load is being synthesized in compatability mode. A synthesis/simulation mismatch is possible. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal wre_reg. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal sda_out_en. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal in_reg_enable. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal di_reg[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal clken. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal bit_counter[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : I2C_SLAVE_TOP.v(362) | Feedback mux created for signal ad_reg[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CL190 : I2C_SLAVE_TOP.v(288) | Optimizing register bit in_reg[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : I2C_SLAVE_TOP.v(288) | Pruning register bit 8 of in_reg[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : gw1n.v(603) | Synthesizing module SP in library work. Running optimization stage 1 on SP ....... @N:CG364 : I2C_SLAVE_TOP.v(9) | Synthesizing module I2C_SLAVE_Top in library work. @W:CS263 : I2C_SLAVE_TOP.v(62) | Port-width mismatch for port DI. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port. @W:CS263 : I2C_SLAVE_TOP.v(61) | Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on I2C_SLAVE_Top ....... @N:CG364 : gw_i2c_slave.v(5) | Synthesizing module gw_i2c_slave in library work. Running optimization stage 1 on gw_i2c_slave ....... @W:CL271 : gw_i2c_slave.v(45) | Pruning unused bits 7 to 6 of delay_rst_5[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Running optimization stage 2 on gw_i2c_slave ....... Running optimization stage 2 on I2C_SLAVE_Top ....... Running optimization stage 2 on SP ....... Running optimization stage 2 on i2c_slave ....... @W:CL138 : I2C_SLAVE_TOP.v(362) | Removing register 'data_len_reg' because it is only assigned 0 or its original value. Running optimization stage 2 on Gowin_PLL ....... Running optimization stage 2 on PLL ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 10:32:56 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 10:32:56 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 10:32:56 2019 ###########################################################] ###########################################################[ Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q4p1, Build 157R, Built Mar 12 2019 09:11:06 @N: : | Running in 64-bit mode File D:\IP release\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_Release\Gowin_I2C_Slave_refDesign\gw_i2c_slave\impl\synthesize\rev_1\synwork\gw_i2c_slave_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 17 10:32:58 2019 ###########################################################] Premap Report # Tue Sep 17 10:32:59 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: gw_i2c_slave_scck.rpt Printing clock summary report in "D:\gw_i2c_slave\impl\synthesize\rev_1\gw_i2c_slave_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design @W:FX707 : i2c_slave_top.v(362) | Register u_i2c_slave_top.u_i2c_slave.nstate[0] has both asynchronous set and reset. Your design may not work on the board. GoWin recommends you change your RTL. This warning is only issued once, although it may apply to other registers as well. @W:BN680 : i2c_slave_top.v(300) | Found conflicting initial value on the register sda_reg. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. @W:BN680 : i2c_slave_top.v(311) | Found conflicting initial value on the register scl_reg_dly. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. @W:BN680 : i2c_slave_top.v(311) | Found conflicting initial value on the register scl_reg. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. @W:BN680 : i2c_slave_top.v(300) | Found conflicting initial value on the register sda_reg_dly. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. @W:FX474 : | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) @N:MF578 : | Incompatible asynchronous control logic preventing generated clock conversion. Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------- 0 - Gowin_PLL|clkout_inferred_clock 107.5 MHz 9.298 inferred Autoconstr_clkgroup_0 108 ====================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------------------------------------------------------- Gowin_PLL|clkout_inferred_clock 108 your_instance_name.pll_inst.CLKOUT(PLL) clk_en_0.C - - ========================================================================================================================================= @W:MT529 : i2c_slave_top.v(362) | Found inferred clock Gowin_PLL|clkout_inferred_clock which controls 108 sequential elements including u_i2c_slave_top.u_i2c_slave.nstate_0[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 5 gated/generated clock tree(s) driving 112 clock pin(s) of sequential element(s) 0 instances converted, 112 sequential instances remain driven by gated/generated clocks =================================================================================== Gated/Generated Clocks =================================================================================== Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId_0_1 your_instance_name.pll_inst.CLKOUT PLL 108 counter0[0] Black box on clock path ClockId_0_2 u_i2c_slave_top.u_i2c_slave.un1_in_reg11.OUT and 1 u_i2c_slave_top.u_i2c_slave.nstate_17_0 Clock source is invalid for GCC ClockId_0_3 u_i2c_slave_top.u_i2c_slave.un1_in_reg11_1.OUT and 1 u_i2c_slave_top.u_i2c_slave.nstate_12_0 Clock source is invalid for GCC ClockId_0_4 u_i2c_slave_top.u_i2c_slave.un1_in_reg11_2.OUT and 1 u_i2c_slave_top.u_i2c_slave.nstate_7_0 Clock source is invalid for GCC ClockId_0_5 u_i2c_slave_top.u_i2c_slave.un1_in_reg11_3.OUT and 1 u_i2c_slave_top.u_i2c_slave.nstate_2_0 Clock source is invalid for GCC ============================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\gw_i2c_slave\impl\synthesize\rev_1\gw_i2c_slave.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 191MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 105MB peak: 191MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 17 10:33:00 2019 ###########################################################] Map & Optimize Report # Tue Sep 17 10:33:01 2019 Copyright (C) 1994-2019 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-SP1-1-Beta1 Install: D:\GOWIN SW\v191_01Beta\Gowin\Gowin_V1.9.1.01Beta\SynplifyPro OS: Windows 6.1 Hostname: Desktop-2019KKU Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw2018q4p1, Build 001R, Built Mar 29 2019 09:46:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[0]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_17. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[1]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_12. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[2]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_7. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[3]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_2. @N:FX493 : | Applying initial value "0000" on instance u_i2c_slave_top.u_i2c_slave.cstate[3:0]. @N:FX493 : | Applying initial value "000000000" on instance u_i2c_slave_top.u_i2c_slave.addr_len_reg[8:0]. @N:FX493 : | Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.ad_reg[7:0]. @N:FX493 : | Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.word_address[7:0]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.clken. @N:FX493 : | Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.in_reg[7:0]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.in_reg_enable. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.sda_out_en. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.int_reg. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.ack_flag. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.slave_addr_flag. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.word_add_flag. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.w_r_flag. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.is_write. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.sda_reg. @N:FX493 : | Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.di_reg[7:0]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.wre_reg. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.stop_condition. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.start_condition. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_negedge. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_posedge. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_reg_dly. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_reg. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.sda_reg_dly. @N:FX493 : | Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.sp_out_reg[7:0]. @N:FX493 : | Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.clken_reg. @N:FX493 : | Applying initial value "0000" on instance u_i2c_slave_top.u_i2c_slave.bit_counter[3:0]. @N:FX493 : | Applying initial value "0000000000000000" on instance counter0[15:0]. @N:FX493 : | Applying initial value "000000" on instance delay_rst[5:0]. @N:FX493 : | Applying initial value "0" on instance clk_en. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 191MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 194MB peak: 195MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 195MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 195MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 215MB peak: 217MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -5.29ns 228 / 107 2 0h:00m:01s -5.29ns 223 / 107 @N:FX271 : i2c_slave_top.v(362) | Replicating instance u_i2c_slave_top.u_i2c_slave.bit_counter[0] (in view: work.gw_i2c_slave(verilog)) with 16 loads 1 time to improve timing. @N:FX271 : i2c_slave_top.v(362) | Replicating instance u_i2c_slave_top.u_i2c_slave.bit_counter[3] (in view: work.gw_i2c_slave(verilog)) with 15 loads 1 time to improve timing. Timing driven replication report Added 2 Registers via timing driven replication Added 2 LUTs via timing driven replication 3 0h:00m:01s -5.23ns 225 / 109 4 0h:00m:01s -5.23ns 225 / 109 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 216MB peak: 217MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 216MB peak: 217MB) Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 144MB peak: 217MB) Writing Analyst data base D:\gw_i2c_slave\impl\synthesize\rev_1\synwork\gw_i2c_slave_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 215MB peak: 217MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 214MB peak: 217MB) Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB) @W:MT246 : gowin_pll.v(21) | Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Gowin_PLL|clkout_inferred_clock with period 11.96ns. Please declare a user-defined clock on net your_instance_name.clkout_50m. ##### START OF TIMING REPORT #####[ # Timing report written on Tue Sep 17 10:33:05 2019 # Top view: gw_i2c_slave Requested Frequency: 83.6 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -2.110 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------- Gowin_PLL|clkout_inferred_clock 83.6 MHz 71.1 MHz 11.957 14.067 -2.110 inferred Autoconstr_clkgroup_0 System 100.0 MHz NA 10.000 NA 10.803 system system_clkgroup ========================================================================================================================================= Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------- System Gowin_PLL|clkout_inferred_clock | 11.957 10.803 | No paths - | No paths - | No paths - Gowin_PLL|clkout_inferred_clock System | 11.957 10.447 | No paths - | No paths - | No paths - Gowin_PLL|clkout_inferred_clock Gowin_PLL|clkout_inferred_clock | 11.957 -2.110 | No paths - | No paths - | No paths - ========================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Gowin_PLL|clkout_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------- u_i2c_slave_top.u_i2c_slave.bit_counter[2] Gowin_PLL|clkout_inferred_clock DFFRE Q un16_ac0_4 0.367 -2.110 u_i2c_slave_top.u_i2c_slave.bit_counter[1] Gowin_PLL|clkout_inferred_clock DFFRE Q un16_ac0_2 0.367 -2.043 u_i2c_slave_top.u_i2c_slave.bit_counter[0] Gowin_PLL|clkout_inferred_clock DFFRE Q un16_c1 0.367 -1.833 u_i2c_slave_top.u_i2c_slave.w_r_flag_0 Gowin_PLL|clkout_inferred_clock DFFCE Q w_r_flag 0.367 -1.698 u_i2c_slave_top.u_i2c_slave.scl_negedge_0 Gowin_PLL|clkout_inferred_clock DFFC Q scl_negedge 0.367 -1.570 u_i2c_slave_top.u_i2c_slave.start_condition_0 Gowin_PLL|clkout_inferred_clock DFFC Q start_condition 0.367 -1.564 delay_rst[3] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst[3] 0.367 -1.484 u_i2c_slave_top.u_i2c_slave.ack_flag_0 Gowin_PLL|clkout_inferred_clock DFFCE Q ack_flag 0.367 -1.442 delay_rst[0] Gowin_PLL|clkout_inferred_clock DFFE Q delay_rst[0] 0.367 -1.417 u_i2c_slave_top.u_i2c_slave.stop_condition_0 Gowin_PLL|clkout_inferred_clock DFFC Q stop_condition 0.367 -1.287 ============================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------ u_i2c_slave_top.u_i2c_slave.word_address[6] Gowin_PLL|clkout_inferred_clock DFFC D word_address_9[6] 11.824 -2.110 u_i2c_slave_top.u_i2c_slave.cstate[2] Gowin_PLL|clkout_inferred_clock DFFC D cstate_15[2] 11.824 -1.570 u_i2c_slave_top.u_i2c_slave.bit_counter[3] Gowin_PLL|clkout_inferred_clock DFFRE CE un1_bit_counter_6_c3 11.824 -1.484 u_i2c_slave_top.u_i2c_slave.bit_counter_fast[3] Gowin_PLL|clkout_inferred_clock DFFRE CE un1_bit_counter_6_c3 11.824 -1.484 u_i2c_slave_top.u_i2c_slave.bit_counter[0] Gowin_PLL|clkout_inferred_clock DFFRE RESET un1_bit_counter_1_sqmuxa 11.824 -0.546 u_i2c_slave_top.u_i2c_slave.bit_counter[1] Gowin_PLL|clkout_inferred_clock DFFRE RESET un1_bit_counter_1_sqmuxa 11.824 -0.546 u_i2c_slave_top.u_i2c_slave.bit_counter[2] Gowin_PLL|clkout_inferred_clock DFFRE RESET un1_bit_counter_1_sqmuxa 11.824 -0.546 u_i2c_slave_top.u_i2c_slave.bit_counter[3] Gowin_PLL|clkout_inferred_clock DFFRE RESET un1_bit_counter_1_sqmuxa 11.824 -0.546 u_i2c_slave_top.u_i2c_slave.bit_counter_fast[0] Gowin_PLL|clkout_inferred_clock DFFRE RESET un1_bit_counter_1_sqmuxa 11.824 -0.546 u_i2c_slave_top.u_i2c_slave.bit_counter_fast[3] Gowin_PLL|clkout_inferred_clock DFFRE RESET un1_bit_counter_1_sqmuxa 11.824 -0.546 ============================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 11.957 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.824 - Propagation time: 13.934 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.110 Number of logic level(s): 7 Starting point: u_i2c_slave_top.u_i2c_slave.bit_counter[2] / Q Ending point: u_i2c_slave_top.u_i2c_slave.word_address[6] / D The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ u_i2c_slave_top.u_i2c_slave.bit_counter[2] DFFRE Q Out 0.367 0.367 - un16_ac0_4 Net - - 1.082 - 18 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 I1 In - 1.449 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 F Out 1.099 2.548 - in_reg_enable26_a0_4 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 I1 In - 3.314 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 F Out 1.099 4.413 - in_reg_enable26 Net - - 1.082 - 11 u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 I2 In - 5.495 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 F Out 0.822 6.317 - un1_clken18_1_1 Net - - 1.021 - 3 u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 I3 In - 7.338 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 F Out 0.626 7.964 - un1_clken18_1 Net - - 1.021 - 6 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 I0 In - 8.985 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 F Out 1.032 10.017 - un1_word_address_c5 Net - - 1.021 - 2 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 I0 In - 11.038 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 F Out 1.032 12.069 - un1_word_address_c6 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 I1 In - 12.835 - u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 F Out 1.099 13.934 - word_address_9[6] Net - - 0.000 - 1 u_i2c_slave_top.u_i2c_slave.word_address[6] DFFC D In - 13.934 - ================================================================================================================== Total path delay (propagation time + setup) of 14.067 is 7.309(52.0%) logic and 6.758(48.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 11.957 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.824 - Propagation time: 13.867 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -2.043 Number of logic level(s): 7 Starting point: u_i2c_slave_top.u_i2c_slave.bit_counter[1] / Q Ending point: u_i2c_slave_top.u_i2c_slave.word_address[6] / D The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ u_i2c_slave_top.u_i2c_slave.bit_counter[1] DFFRE Q Out 0.367 0.367 - un16_ac0_2 Net - - 1.082 - 16 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 I0 In - 1.449 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 F Out 1.032 2.481 - in_reg_enable26_a0_4 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 I1 In - 3.247 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 F Out 1.099 4.346 - in_reg_enable26 Net - - 1.082 - 11 u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 I2 In - 5.428 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 F Out 0.822 6.250 - un1_clken18_1_1 Net - - 1.021 - 3 u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 I3 In - 7.271 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 F Out 0.626 7.897 - un1_clken18_1 Net - - 1.021 - 6 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 I0 In - 8.918 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 F Out 1.032 9.950 - un1_word_address_c5 Net - - 1.021 - 2 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 I0 In - 10.970 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 F Out 1.032 12.002 - un1_word_address_c6 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 I1 In - 12.768 - u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 F Out 1.099 13.867 - word_address_9[6] Net - - 0.000 - 1 u_i2c_slave_top.u_i2c_slave.word_address[6] DFFC D In - 13.867 - ================================================================================================================== Total path delay (propagation time + setup) of 14.000 is 7.242(51.7%) logic and 6.758(48.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 11.957 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.824 - Propagation time: 13.657 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.833 Number of logic level(s): 7 Starting point: u_i2c_slave_top.u_i2c_slave.bit_counter[0] / Q Ending point: u_i2c_slave_top.u_i2c_slave.word_address[6] / D The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ u_i2c_slave_top.u_i2c_slave.bit_counter[0] DFFRE Q Out 0.367 0.367 - un16_c1 Net - - 1.082 - 19 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 I2 In - 1.449 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 F Out 0.822 2.271 - in_reg_enable26_a0_4 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 I1 In - 3.037 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 F Out 1.099 4.136 - in_reg_enable26 Net - - 1.082 - 11 u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 I2 In - 5.218 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 F Out 0.822 6.040 - un1_clken18_1_1 Net - - 1.021 - 3 u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 I3 In - 7.061 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 F Out 0.626 7.687 - un1_clken18_1 Net - - 1.021 - 6 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 I0 In - 8.708 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 F Out 1.032 9.740 - un1_word_address_c5 Net - - 1.021 - 2 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 I0 In - 10.761 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 F Out 1.032 11.793 - un1_word_address_c6 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 I1 In - 12.558 - u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 F Out 1.099 13.657 - word_address_9[6] Net - - 0.000 - 1 u_i2c_slave_top.u_i2c_slave.word_address[6] DFFC D In - 13.657 - ================================================================================================================== Total path delay (propagation time + setup) of 13.790 is 7.032(51.0%) logic and 6.758(49.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 11.957 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.824 - Propagation time: 13.522 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.698 Number of logic level(s): 7 Starting point: u_i2c_slave_top.u_i2c_slave.w_r_flag_0 / Q Ending point: u_i2c_slave_top.u_i2c_slave.word_address[6] / D The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ u_i2c_slave_top.u_i2c_slave.w_r_flag_0 DFFCE Q Out 0.367 0.367 - w_r_flag Net - - 1.143 - 23 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 I3 In - 1.510 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0_4 LUT4 F Out 0.626 2.136 - in_reg_enable26_a0_4 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 I1 In - 2.902 - u_i2c_slave_top.u_i2c_slave.in_reg_enable26_a0 LUT4 F Out 1.099 4.001 - in_reg_enable26 Net - - 1.082 - 11 u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 I2 In - 5.083 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1_1 LUT4 F Out 0.822 5.905 - un1_clken18_1_1 Net - - 1.021 - 3 u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 I3 In - 6.926 - u_i2c_slave_top.u_i2c_slave.un1_clken18_1 LUT4 F Out 0.626 7.552 - un1_clken18_1 Net - - 1.021 - 6 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 I0 In - 8.573 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_7 LUT4 F Out 1.032 9.605 - un1_word_address_c5 Net - - 1.021 - 2 u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 I0 In - 10.626 - u_i2c_slave_top.u_i2c_slave.un1_word_address_ac0_9 LUT2 F Out 1.032 11.658 - un1_word_address_c6 Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 I1 In - 12.423 - u_i2c_slave_top.u_i2c_slave.word_address_9[6] LUT4 F Out 1.099 13.522 - word_address_9[6] Net - - 0.000 - 1 u_i2c_slave_top.u_i2c_slave.word_address[6] DFFC D In - 13.522 - ================================================================================================================== Total path delay (propagation time + setup) of 13.655 is 6.836(50.1%) logic and 6.819(49.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 11.957 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.824 - Propagation time: 13.394 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.570 Number of logic level(s): 7 Starting point: u_i2c_slave_top.u_i2c_slave.scl_negedge_0 / Q Ending point: u_i2c_slave_top.u_i2c_slave.cstate[2] / D The start point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ u_i2c_slave_top.u_i2c_slave.scl_negedge_0 DFFC Q Out 0.367 0.367 - scl_negedge Net - - 1.082 - 13 u_i2c_slave_top.u_i2c_slave.un1_scl_negedge_3_0 LUT2 I1 In - 1.449 - u_i2c_slave_top.u_i2c_slave.un1_scl_negedge_3_0 LUT2 F Out 1.099 2.548 - un1_scl_negedge_3_0 Net - - 1.021 - 5 u_i2c_slave_top.u_i2c_slave.un1_cstate5_2 LUT3 I1 In - 3.569 - u_i2c_slave_top.u_i2c_slave.un1_cstate5_2 LUT3 F Out 1.099 4.668 - un1_cstate5_2 Net - - 1.021 - 3 u_i2c_slave_top.u_i2c_slave.cstate_3_sqmuxa_2 LUT4 I2 In - 5.689 - u_i2c_slave_top.u_i2c_slave.cstate_3_sqmuxa_2 LUT4 F Out 0.822 6.511 - cstate_3_sqmuxa_2 Net - - 1.021 - 3 u_i2c_slave_top.u_i2c_slave.cstate_cnst_i_a2_3_1[2] LUT4 I2 In - 7.532 - u_i2c_slave_top.u_i2c_slave.cstate_cnst_i_a2_3_1[2] LUT4 F Out 0.822 8.354 - cstate_cnst_i_a2_3_1[2] Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.cstate_cnst_i_a2_3_2[2] LUT4 I1 In - 9.120 - u_i2c_slave_top.u_i2c_slave.cstate_cnst_i_a2_3_2[2] LUT4 F Out 1.099 10.219 - cstate_cnst_i_a2_3_2[2] Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.cstate_cnst_i_a2_3[2] LUT4 I2 In - 10.984 - u_i2c_slave_top.u_i2c_slave.cstate_cnst_i_a2_3[2] LUT4 F Out 0.822 11.806 - cstate_cnst_i_a2_3[2] Net - - 0.766 - 1 u_i2c_slave_top.u_i2c_slave.cstate_0[2] LUT4 I2 In - 12.572 - u_i2c_slave_top.u_i2c_slave.cstate_0[2] LUT4 F Out 0.822 13.394 - cstate_15[2] Net - - 0.000 - 1 u_i2c_slave_top.u_i2c_slave.cstate[2] DFFC D In - 13.394 - ================================================================================================================== Total path delay (propagation time + setup) of 13.527 is 7.085(52.4%) logic and 6.442(47.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- u_i2c_slave_top.u_i2c_slave.bit_counter_0_0[0] System INV O N_35_0 0.000 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter_0_0[2] System INV O N_31_0 0.000 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter_0_0[3] System INV O N_29_0 0.000 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter_0_fast_0[0] System INV O N_35_fast_0 0.000 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter_0_fast_0[3] System INV O N_29_fast_0 0.000 10.803 u_i2c_slave_top.u_i2c_slave.mem_wre_i System INV O mem_wre_i 0.000 10.803 u_i2c_slave_top.u_i2c_slave.w_r_flag_i System INV O w_r_flag_i 0.000 10.803 ========================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- u_i2c_slave_top.u_i2c_slave.bit_counter[0] System DFFRE D N_35_0 11.824 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter[2] System DFFRE D N_31_0 11.824 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter[3] System DFFRE D N_29_0 11.824 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter_fast[0] System DFFRE D N_35_fast_0 11.824 10.803 u_i2c_slave_top.u_i2c_slave.bit_counter_fast[3] System DFFRE D N_29_fast_0 11.824 10.803 u_i2c_slave_top.u_i2c_slave.sp_out_reg[0] System DFFE CE mem_wre_i 11.824 10.803 u_i2c_slave_top.u_i2c_slave.sp_out_reg[1] System DFFE CE mem_wre_i 11.824 10.803 u_i2c_slave_top.u_i2c_slave.sp_out_reg[2] System DFFE CE mem_wre_i 11.824 10.803 u_i2c_slave_top.u_i2c_slave.sp_out_reg[3] System DFFE CE mem_wre_i 11.824 10.803 u_i2c_slave_top.u_i2c_slave.sp_out_reg[4] System DFFE CE mem_wre_i 11.824 10.803 ======================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 11.957 - Setup time: 0.133 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.824 - Propagation time: 1.021 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 10.803 Number of logic level(s): 0 Starting point: u_i2c_slave_top.u_i2c_slave.bit_counter_0_0[0] / O Ending point: u_i2c_slave_top.u_i2c_slave.bit_counter[0] / D The start point is clocked by System [rising] The end point is clocked by Gowin_PLL|clkout_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- u_i2c_slave_top.u_i2c_slave.bit_counter_0_0[0] INV O Out 0.000 0.000 - N_35_0 Net - - 1.021 - 1 u_i2c_slave_top.u_i2c_slave.bit_counter[0] DFFRE D In - 1.021 - ============================================================================================================== Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB) Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB) --------------------------------------- Resource Usage Report for gw_i2c_slave Mapping to part: gw1n_4lqfp144-6 Cell usage: ALU 25 uses DFF 12 uses DFFC 33 uses DFFCE 14 uses DFFE 34 uses DFFP 4 uses DFFR 6 uses DFFRE 6 uses DLCE 4 uses GSR 1 use INV 7 uses MUX2_LUT5 6 uses MUX2_LUT6 2 uses PLL 1 use SP 1 use LUT2 28 uses LUT3 52 uses LUT4 114 uses I/O ports: 7 I/O primitives: 7 IBUF 3 uses IOBUF 1 use OBUF 3 uses I/O Register bits: 0 Register bits not including I/Os: 109 of 3456 (3%) RAM/ROM usage summary Block Rams : 1 of 10 (10%) Total load per clock: Gowin_PLL|clkout_inferred_clock: 110 @S |Mapping Summary: Total LUTs: 194 (4%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 41MB peak: 217MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime # Tue Sep 17 10:33:05 2019 ###########################################################]