@W: FX707 :"d:\gw_i2c_slave\src\i2c_slave_top.v":362:4:362:9|Register u_i2c_slave_top.u_i2c_slave.nstate[0] has both asynchronous set and reset. Your design may not work on the board. GoWin recommends you change your RTL. This warning is only issued once, although it may apply to other registers as well.
@W: BN680 :"d:\gw_i2c_slave\src\i2c_slave_top.v":300:4:300:9|Found conflicting initial value on the register sda_reg. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. 
@W: BN680 :"d:\gw_i2c_slave\src\i2c_slave_top.v":311:4:311:9|Found conflicting initial value on the register scl_reg_dly. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. 
@W: BN680 :"d:\gw_i2c_slave\src\i2c_slave_top.v":311:4:311:9|Found conflicting initial value on the register scl_reg. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. 
@W: BN680 :"d:\gw_i2c_slave\src\i2c_slave_top.v":300:4:300:9|Found conflicting initial value on the register sda_reg_dly. Specified technology does not support initial value of 0 on register with asynchronous set. To resolve, update the RTL with correct inital value. 
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: MT529 :"d:\gw_i2c_slave\src\i2c_slave_top.v":362:4:362:9|Found inferred clock Gowin_PLL|clkout_inferred_clock which controls 108 sequential elements including u_i2c_slave_top.u_i2c_slave.nstate_0[0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
