@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MT206 |Auto Constrain mode is enabled
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[0].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_17.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[1].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_12.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[2].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_7.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate[3].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.nstate_2.
@N: FX493 |Applying initial value "0000" on instance u_i2c_slave_top.u_i2c_slave.cstate[3:0].
@N: FX493 |Applying initial value "000000000" on instance u_i2c_slave_top.u_i2c_slave.addr_len_reg[8:0].
@N: FX493 |Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.ad_reg[7:0].
@N: FX493 |Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.word_address[7:0].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.clken.
@N: FX493 |Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.in_reg[7:0].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.in_reg_enable.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.sda_out_en.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.int_reg.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.ack_flag.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.slave_addr_flag.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.word_add_flag.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.w_r_flag.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.is_write.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.sda_reg.
@N: FX493 |Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.di_reg[7:0].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.wre_reg.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.stop_condition.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.start_condition.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_negedge.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_posedge.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_reg_dly.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.scl_reg.
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.sda_reg_dly.
@N: FX493 |Applying initial value "00000000" on instance u_i2c_slave_top.u_i2c_slave.sp_out_reg[7:0].
@N: FX493 |Applying initial value "0" on instance u_i2c_slave_top.u_i2c_slave.clken_reg.
@N: FX493 |Applying initial value "0000" on instance u_i2c_slave_top.u_i2c_slave.bit_counter[3:0].
@N: FX493 |Applying initial value "0000000000000000" on instance counter0[15:0].
@N: FX493 |Applying initial value "000000" on instance delay_rst[5:0].
@N: FX493 |Applying initial value "0" on instance clk_en.
@N: FX271 :"d:\gw_i2c_slave\src\i2c_slave_top.v":362:4:362:9|Replicating instance u_i2c_slave_top.u_i2c_slave.bit_counter[0] (in view: work.gw_i2c_slave(verilog)) with 16 loads 1 time to improve timing.
@N: FX271 :"d:\gw_i2c_slave\src\i2c_slave_top.v":362:4:362:9|Replicating instance u_i2c_slave_top.u_i2c_slave.bit_counter[3] (in view: work.gw_i2c_slave(verilog)) with 15 loads 1 time to improve timing.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
