@W: CL169 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":362:4:362:9|Pruning unused register is_continue. Make sure that there are no unused intermediate registers.
@W: CL271 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":362:4:362:9|Pruning unused bits 7 to 0 of data_len_reg[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":288:4:288:9|Optimizing register bit in_reg[8] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":288:4:288:9|Pruning register bit 8 of in_reg[8:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CS263 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":62:24:62:40|Port-width mismatch for port DI. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port.
@W: CS263 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":61:24:61:40|Port-width mismatch for port DO. The port definition is 32 bits, but the actual port connection bit width is 8. Adjust either the definition or the instantiation of this port.
@W: CL271 :"D:\gw_i2c_slave\src\gw_i2c_slave.v":45:0:45:5|Pruning unused bits 7 to 6 of delay_rst_5[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL138 :"D:\gw_i2c_slave\src\I2C_SLAVE_TOP.v":362:4:362:9|Removing register 'data_len_reg' because it is only assigned 0 or its original value.

