Timing Messages

Report Title	Timing Analysis Report
Design File	E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\impl\gwsynthesis\gw_i2c_slave.vg
Physical Constraints File	E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\i2c_slave.cst
Timing Constraint File	E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\gw_i2c_slave.sdc
Tool Version	V1.9.10.03 (64-bit)
Part Number	GW1N-LV4LQ144C6/I5
Device	GW1N-4
Created Time	Tue Sep 24 15:03:45 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	579
Numbers of Endpoints Analyzed	277
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	CLK_50M	Base	20.000	50.000	0.000	10.000			clk_50m
2	your_instance_name/pll_inst/CLKOUT.default_gen_clk	Generated	20.000	50.000	0.000	10.000	clk_50m_ibuf/I	CLK_50M	your_instance_name/pll_inst/CLKOUT
3	your_instance_name/pll_inst/CLKOUTP.default_gen_clk	Generated	20.000	50.000	0.000	10.000	clk_50m_ibuf/I	CLK_50M	your_instance_name/pll_inst/CLKOUTP
4	your_instance_name/pll_inst/CLKOUTD.default_gen_clk	Generated	40.000	25.000	0.000	20.000	clk_50m_ibuf/I	CLK_50M	your_instance_name/pll_inst/CLKOUTD
5	your_instance_name/pll_inst/CLKOUTD3.default_gen_clk	Generated	60.000	16.667	0.000	30.000	clk_50m_ibuf/I	CLK_50M	your_instance_name/pll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	your_instance_name/pll_inst/CLKOUT.default_gen_clk	50.000(MHz)	91.767(MHz)	5	TOP

No timing paths to get frequency of CLK_50M!

No timing paths to get frequency of your_instance_name/pll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/pll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of your_instance_name/pll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
CLK_50M	Setup	0.000	0
CLK_50M	Hold	0.000	0
your_instance_name/pll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
your_instance_name/pll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
your_instance_name/pll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
your_instance_name/pll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
your_instance_name/pll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
your_instance_name/pll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
your_instance_name/pll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/pll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	9.103	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	10.854
2	9.899	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.701
3	9.940	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.660
4	9.966	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.634
5	10.346	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.254
6	10.440	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.160
7	10.758	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.199
8	10.758	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.199
9	10.796	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.160
10	10.796	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_7_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.160
11	10.837	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.120
12	10.843	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_1_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.114
13	10.874	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.083
14	10.874	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.083
15	10.888	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_3_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	9.069
16	11.169	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_5_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.788
17	11.171	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.786
18	11.171	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.786
19	11.213	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.744
20	11.213	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_1_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.744
21	11.213	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.744
22	11.213	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.744
23	11.213	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_5_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.744
24	11.213	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_6_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.744
25	11.222	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	8.734

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	u_i2c_slave_top/u_i2c_slave/nstate_2_s1/Q	u_i2c_slave_top/u_i2c_slave/nstate_2_s1/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
2	0.708	counter0_0_s0/Q	counter0_0_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
3	0.710	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/Q	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.710
4	0.711	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/Q	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.711
5	0.711	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.711
6	0.716	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.716
7	0.721	u_i2c_slave_top/u_i2c_slave/di_reg_2_s0/Q	u_i2c_slave_top/gw_sp/DI[2]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.881
8	0.721	u_i2c_slave_top/u_i2c_slave/di_reg_1_s0/Q	u_i2c_slave_top/gw_sp/DI[1]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.881
9	0.727	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0/Q	u_i2c_slave_top/gw_sp/AD[7]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.881
10	0.727	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0/Q	u_i2c_slave_top/gw_sp/AD[5]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.881
11	0.727	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0/Q	u_i2c_slave_top/gw_sp/AD[3]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.881
12	0.730	counter0_2_s0/Q	counter0_2_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.730
13	0.730	counter0_6_s0/Q	counter0_6_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.730
14	0.730	counter0_8_s0/Q	counter0_8_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.730
15	0.730	counter0_12_s0/Q	counter0_12_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.730
16	0.730	counter0_14_s0/Q	counter0_14_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.730
17	0.835	clk_en_s0/Q	delay_rst_1_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.847
18	0.835	clk_en_s0/Q	delay_rst_2_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.847
19	0.835	clk_en_s0/Q	delay_rst_3_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.847
20	0.835	clk_en_s0/Q	delay_rst_4_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.847
21	0.835	clk_en_s0/Q	delay_rst_5_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.847
22	0.853	counter0_1_s0/Q	counter0_1_s0/D	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.853
23	0.864	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.877
24	0.864	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.877
25	0.864	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CE	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.877

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	12.840	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	7.117
2	13.478	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/scl_reg_s0/PRESET	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	6.478
3	13.640	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/w_r_flag_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	6.317
4	13.798	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	6.159
5	13.798	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_0_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	6.159
6	13.809	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/sda_reg_s0/PRESET	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	6.148
7	13.812	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	6.145
8	14.115	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.842
9	14.115	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/cstate_0_s1/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.842
10	14.129	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/cstate_3_s1/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.828
11	14.134	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/cstate_2_s1/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.823
12	14.277	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/word_add_flag_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.680
13	14.277	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.680
14	14.277	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.680
15	14.277	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.680
16	14.277	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_5_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.680
17	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
18	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
19	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
20	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
21	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
22	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
23	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
24	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670
25	14.287	delay_rst_0_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	20.000	0.000	5.670

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.785	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/scl_negedge_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.798
2	1.785	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/scl_reg_dly_s0/PRESET	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	1.798
3	2.056	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.069
4	2.056	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.069
5	2.064	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.076
6	2.085	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.098
7	2.093	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.105
8	2.093	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/cstate_1_s1/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.105
9	2.093	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/scl_posedge_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.105
10	2.519	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/is_write_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.531
11	2.519	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.531
12	2.519	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_1_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.531
13	2.519	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_6_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.531
14	2.519	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/in_reg_0_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.531
15	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
16	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
17	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
18	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
19	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
20	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
21	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
22	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
23	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
24	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_5_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537
25	2.525	delay_rst_1_s0/Q	u_i2c_slave_top/u_i2c_slave/word_address_7_s0/CLEAR	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	2.537

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	counter0_14_s0
2	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	counter0_12_s0
3	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	counter0_8_s0
4	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	counter0_0_s0
5	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	u_i2c_slave_top/u_i2c_slave/sp_out_reg_1_s0
6	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0
7	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0
8	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	u_i2c_slave_top/u_i2c_slave/sp_out_reg_2_s0
9	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	u_i2c_slave_top/u_i2c_slave/int_reg_s0
10	8.672	9.922	1.250	Low Pulse Width	your_instance_name/pll_inst/CLKOUT.default_gen_clk	u_i2c_slave_top/u_i2c_slave/word_address_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	9.103
Data Arrival Time	14.534
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/int_reg_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
11.441	0.815	tNET	FF	1	R7C9[3][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s4/I1
12.502	1.061	tINS	FR	1	R7C9[3][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s4/F
14.534	2.033	tNET	RR	1	IOB19[B]	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	IOB19[B]	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CLK
23.637	-0.043	tSu		1	IOB19[B]	u_i2c_slave_top/u_i2c_slave/int_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.412, 31.436%; route: 6.983, 64.341%; tC2Q: 0.458, 4.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path2

Path Summary:

Slack	9.899
Data Arrival Time	13.381
Data Required Time	23.280
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
8.047	1.333	tNET	FF	1	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/I0
9.146	1.099	tINS	FF	3	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/F
10.440	1.294	tNET	FF	1	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/I2
11.472	1.032	tINS	FF	4	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/F
12.282	0.810	tNET	FF	1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1028_s29/I0
13.381	1.099	tINS	FF	1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1028_s29/F
13.381	0.000	tNET	FF	1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/CLK
23.280	-0.400	tSu		1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 4.329, 44.625%; route: 4.913, 50.650%; tC2Q: 0.458, 4.725%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path3

Path Summary:

Slack	9.940
Data Arrival Time	13.341
Data Required Time	23.280
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
8.047	1.333	tNET	FF	1	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/I0
9.146	1.099	tINS	FF	3	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/F
10.440	1.294	tNET	FF	1	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/I2
11.472	1.032	tINS	FF	4	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/F
12.309	0.836	tNET	FF	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s30/I0
13.341	1.032	tINS	FF	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s30/F
13.341	0.000	tNET	FF	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/CLK
23.280	-0.400	tSu		1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 4.262, 44.119%; route: 4.940, 51.136%; tC2Q: 0.458, 4.745%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path4

Path Summary:

Slack	9.966
Data Arrival Time	13.314
Data Required Time	23.280
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
8.047	1.333	tNET	FF	1	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/I0
9.146	1.099	tINS	FF	3	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/F
10.440	1.294	tNET	FF	1	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/I2
11.472	1.032	tINS	FF	4	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/F
12.282	0.810	tNET	FF	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/n1027_s29/I0
13.314	1.032	tINS	FF	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/n1027_s29/F
13.314	0.000	tNET	FF	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/CLK
23.280	-0.400	tSu		1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 4.262, 44.240%; route: 4.913, 51.002%; tC2Q: 0.458, 4.758%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path5

Path Summary:

Slack	10.346
Data Arrival Time	12.935
Data Required Time	23.280
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
8.047	1.333	tNET	FF	1	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/I0
9.146	1.099	tINS	FF	3	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/F
10.440	1.294	tNET	FF	1	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/I2
11.472	1.032	tINS	FF	4	R9C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s31/F
12.309	0.836	tNET	FF	1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/n1029_s29/I0
12.935	0.626	tINS	FF	1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/n1029_s29/F
12.935	0.000	tNET	FF	1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/CLK
23.280	-0.400	tSu		1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.856, 41.668%; route: 4.940, 53.379%; tC2Q: 0.458, 4.953%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path6

Path Summary:

Slack	10.440
Data Arrival Time	12.841
Data Required Time	23.280
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/ack_flag_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
8.047	1.333	tNET	FF	1	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/I0
9.146	1.099	tINS	FF	3	R12C12[2][B]	u_i2c_slave_top/u_i2c_slave/n1035_s23/F
9.956	0.810	tNET	FF	1	R11C13[0][B]	u_i2c_slave_top/u_i2c_slave/n1025_s21/I2
10.988	1.032	tINS	FF	1	R11C13[0][B]	u_i2c_slave_top/u_i2c_slave/n1025_s21/F
11.809	0.821	tNET	FF	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/n1025_s19/I2
12.841	1.032	tINS	FF	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/n1025_s19/F
12.841	0.000	tNET	FF	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLK
23.280	-0.400	tSu		1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 4.262, 46.527%; route: 4.440, 48.470%; tC2Q: 0.458, 5.003%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path7

Path Summary:

Slack	10.758
Data Arrival Time	12.879
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
10.642	0.016	tNET	FF	1	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/I3
11.668	1.026	tINS	FR	8	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/F
12.879	1.212	tNET	RR	1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLK
23.637	-0.043	tSu		1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.377, 36.711%; route: 5.364, 58.307%; tC2Q: 0.458, 4.982%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path8

Path Summary:

Slack	10.758
Data Arrival Time	12.879
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
10.642	0.016	tNET	FF	1	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/I3
11.668	1.026	tINS	FR	8	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/F
12.879	1.212	tNET	RR	1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLK
23.637	-0.043	tSu		1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.377, 36.711%; route: 5.364, 58.307%; tC2Q: 0.458, 4.982%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path9

Path Summary:

Slack	10.796
Data Arrival Time	12.841
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
10.642	0.016	tNET	FF	1	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/I3
11.668	1.026	tINS	FR	8	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/F
12.841	1.173	tNET	RR	1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLK
23.637	-0.043	tSu		1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.377, 36.866%; route: 5.325, 58.131%; tC2Q: 0.458, 5.004%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path10

Path Summary:

Slack	10.796
Data Arrival Time	12.841
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_7_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
10.642	0.016	tNET	FF	1	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/I3
11.668	1.026	tINS	FR	8	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/F
12.841	1.173	tNET	RR	1	R8C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s0/CLK
23.637	-0.043	tSu		1	R8C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.377, 36.866%; route: 5.325, 58.131%; tC2Q: 0.458, 5.004%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path11

Path Summary:

Slack	10.837
Data Arrival Time	12.801
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.624	0.625	tINS	FR	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
11.047	0.423	tNET	RR	1	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/I3
11.672	0.625	tINS	RR	9	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/F
12.801	1.129	tNET	RR	1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLK
23.637	-0.043	tSu		1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.975, 32.620%; route: 5.687, 62.354%; tC2Q: 0.458, 5.026%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path12

Path Summary:

Slack	10.843
Data Arrival Time	12.794
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
10.642	0.016	tNET	FF	1	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/I3
11.668	1.026	tINS	FR	8	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/F
12.794	1.127	tNET	RR	1	R8C8[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C8[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_1_s0/CLK
23.637	-0.043	tSu		1	R8C8[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.377, 37.053%; route: 5.279, 57.918%; tC2Q: 0.458, 5.029%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path13

Path Summary:

Slack	10.874
Data Arrival Time	12.763
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.624	0.625	tINS	FR	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
11.047	0.423	tNET	RR	1	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/I3
11.672	0.625	tINS	RR	9	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/F
12.763	1.091	tNET	RR	1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLK
23.637	-0.043	tSu		1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.975, 32.755%; route: 5.649, 62.199%; tC2Q: 0.458, 5.046%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path14

Path Summary:

Slack	10.874
Data Arrival Time	12.763
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.624	0.625	tINS	FR	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
11.047	0.423	tNET	RR	1	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/I3
11.672	0.625	tINS	RR	9	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/F
12.763	1.091	tNET	RR	1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLK
23.637	-0.043	tSu		1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.975, 32.755%; route: 5.649, 62.199%; tC2Q: 0.458, 5.046%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path15

Path Summary:

Slack	10.888
Data Arrival Time	12.749
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.749	1.123	tNET	RR	1	R8C7[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C7[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_3_s0/CLK
23.637	-0.043	tSu		1	R8C7[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 27.446%; route: 6.121, 67.500%; tC2Q: 0.458, 5.054%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path16

Path Summary:

Slack	11.169
Data Arrival Time	12.469
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.625	0.626	tINS	FF	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
10.642	0.016	tNET	FF	1	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/I3
11.668	1.026	tINS	FR	8	R7C10[3][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s8/F
12.469	0.801	tNET	RR	1	R7C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R7C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_5_s0/CLK
23.637	-0.043	tSu		1	R7C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 3.377, 38.427%; route: 4.953, 56.357%; tC2Q: 0.458, 5.215%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path17

Path Summary:

Slack	11.171
Data Arrival Time	12.466
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.624	0.625	tINS	FR	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
11.047	0.423	tNET	RR	1	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/I3
11.672	0.625	tINS	RR	9	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/F
12.466	0.794	tNET	RR	1	R7C10[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R7C10[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CLK
23.637	-0.043	tSu		1	R7C10[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.975, 33.862%; route: 5.352, 60.922%; tC2Q: 0.458, 5.217%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path18

Path Summary:

Slack	11.171
Data Arrival Time	12.466
Data Required Time	23.637
From	u_i2c_slave_top/u_i2c_slave/stop_condition_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/CLK
4.139	0.458	tC2Q	RF	5	R13C8[0][A]	u_i2c_slave_top/u_i2c_slave/stop_condition_s0/Q
5.615	1.476	tNET	FF	1	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/I0
6.714	1.099	tINS	FF	19	R9C11[2][A]	u_i2c_slave_top/u_i2c_slave/n1037_s8/F
7.903	1.189	tNET	FF	1	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/I2
8.529	0.626	tINS	FF	5	R8C10[1][A]	u_i2c_slave_top/u_i2c_slave/n2020_s2/F
9.999	1.470	tNET	FF	1	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/I3
10.624	0.625	tINS	FR	3	R7C10[2][B]	u_i2c_slave_top/u_i2c_slave/int_reg_s6/F
11.047	0.423	tNET	RR	1	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/I3
11.672	0.625	tINS	RR	9	R7C9[3][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s6/F
12.466	0.794	tNET	RR	1	R8C10[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C10[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CLK
23.637	-0.043	tSu		1	R8C10[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.975, 33.862%; route: 5.352, 60.922%; tC2Q: 0.458, 5.217%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path19

Path Summary:

Slack	11.213
Data Arrival Time	12.424
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.424	0.798	tNET	RR	1	R8C6[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C6[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0/CLK
23.637	-0.043	tSu		1	R8C6[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.466%; route: 5.796, 66.292%; tC2Q: 0.458, 5.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path20

Path Summary:

Slack	11.213
Data Arrival Time	12.424
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.424	0.798	tNET	RR	1	R8C6[0][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C6[0][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_1_s0/CLK
23.637	-0.043	tSu		1	R8C6[0][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.466%; route: 5.796, 66.292%; tC2Q: 0.458, 5.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path21

Path Summary:

Slack	11.213
Data Arrival Time	12.424
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.424	0.798	tNET	RR	1	R8C6[2][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C6[2][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0/CLK
23.637	-0.043	tSu		1	R8C6[2][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.466%; route: 5.796, 66.292%; tC2Q: 0.458, 5.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path22

Path Summary:

Slack	11.213
Data Arrival Time	12.424
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.424	0.798	tNET	RR	1	R8C6[2][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C6[2][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0/CLK
23.637	-0.043	tSu		1	R8C6[2][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.466%; route: 5.796, 66.292%; tC2Q: 0.458, 5.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path23

Path Summary:

Slack	11.213
Data Arrival Time	12.424
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.424	0.798	tNET	RR	1	R8C6[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C6[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_5_s0/CLK
23.637	-0.043	tSu		1	R8C6[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.466%; route: 5.796, 66.292%; tC2Q: 0.458, 5.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path24

Path Summary:

Slack	11.213
Data Arrival Time	12.424
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_6_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.424	0.798	tNET	RR	1	R8C6[1][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C6[1][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_6_s0/CLK
23.637	-0.043	tSu		1	R8C6[1][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.466%; route: 5.796, 66.292%; tC2Q: 0.458, 5.242%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path25

Path Summary:

Slack	11.222
Data Arrival Time	12.415
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.341	2.135	tNET	FF	1	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/I1
10.402	1.061	tINS	FR	9	R7C8[2][B]	u_i2c_slave_top/u_i2c_slave/n2020_s1/F
10.825	0.423	tNET	RR	1	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/I3
11.627	0.802	tINS	RR	8	R8C8[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s5/F
12.415	0.788	tNET	RR	1	R8C5[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C5[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s0/CLK
23.637	-0.043	tSu		1	R8C5[0][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.489, 28.496%; route: 5.787, 66.256%; tC2Q: 0.458, 5.247%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	4.329
Data Required Time	3.621
From	u_i2c_slave_top/u_i2c_slave/nstate_2_s1
To	u_i2c_slave_top/u_i2c_slave/nstate_2_s1
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/nstate_2_s1/CLK
3.954	0.333	tC2Q	RR	2	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/nstate_2_s1/Q
3.957	0.002	tNET	RR	1	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/n1184_s1/I1
4.329	0.372	tINS	RF	1	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/n1184_s1/F
4.329	0.000	tNET	FF	1	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/nstate_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/nstate_2_s1/CLK
3.621	0.000	tHld		1	R13C14[0][A]	u_i2c_slave_top/u_i2c_slave/nstate_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	4.329
Data Required Time	3.621
From	counter0_0_s0
To	counter0_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[0][A]	counter0_0_s0/CLK
3.954	0.333	tC2Q	RR	3	R9C15[0][A]	counter0_0_s0/Q
3.957	0.002	tNET	RR	1	R9C15[0][A]	n37_s2/I0
4.329	0.372	tINS	RF	1	R9C15[0][A]	n37_s2/F
4.329	0.000	tNET	FF	1	R9C15[0][A]	counter0_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[0][A]	counter0_0_s0/CLK
3.621	0.000	tHld		1	R9C15[0][A]	counter0_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path3

Path Summary:

Slack	0.710
Data Arrival Time	4.331
Data Required Time	3.621
From	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2
To	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/CLK
3.954	0.333	tC2Q	RR	6	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/Q
3.959	0.005	tNET	RR	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1031_s11/I2
4.331	0.372	tINS	RF	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1031_s11/F
4.331	0.000	tNET	FF	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/CLK
3.621	0.000	tHld		1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path4

Path Summary:

Slack	0.711
Data Arrival Time	4.332
Data Required Time	3.621
From	u_i2c_slave_top/u_i2c_slave/ack_flag_s2
To	u_i2c_slave_top/u_i2c_slave/ack_flag_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLK
3.954	0.333	tC2Q	RR	8	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/Q
3.960	0.006	tNET	RR	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/n1025_s19/I1
4.332	0.372	tINS	RF	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/n1025_s19/F
4.332	0.000	tNET	FF	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLK
3.621	0.000	tHld		1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path5

Path Summary:

Slack	0.711
Data Arrival Time	4.332
Data Required Time	3.621
From	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2
To	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/CLK
3.954	0.333	tC2Q	RR	9	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/Q
3.960	0.006	tNET	RR	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/n1027_s29/I1
4.332	0.372	tINS	RF	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/n1027_s29/F
4.332	0.000	tNET	FF	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/CLK
3.621	0.000	tHld		1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path6

Path Summary:

Slack	0.716
Data Arrival Time	4.337
Data Required Time	3.621
From	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2
To	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/CLK
3.954	0.333	tC2Q	RR	15	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/Q
3.965	0.011	tNET	RR	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s30/I1
4.337	0.372	tINS	RF	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/n1026_s30/F
4.337	0.000	tNET	FF	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/CLK
3.621	0.000	tHld		1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.372, 51.958%; route: 0.011, 1.484%; tC2Q: 0.333, 46.558%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path7

Path Summary:

Slack	0.721
Data Arrival Time	4.502
Data Required Time	3.781
From	u_i2c_slave_top/u_i2c_slave/di_reg_2_s0
To	u_i2c_slave_top/gw_sp
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C7[1][B]	u_i2c_slave_top/u_i2c_slave/di_reg_2_s0/CLK
3.954	0.333	tC2Q	RR	1	R9C7[1][B]	u_i2c_slave_top/u_i2c_slave/di_reg_2_s0/Q
4.502	0.548	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/CLK
3.781	0.160	tHld		1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path8

Path Summary:

Slack	0.721
Data Arrival Time	4.502
Data Required Time	3.781
From	u_i2c_slave_top/u_i2c_slave/di_reg_1_s0
To	u_i2c_slave_top/gw_sp
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C7[1][A]	u_i2c_slave_top/u_i2c_slave/di_reg_1_s0/CLK
3.954	0.333	tC2Q	RR	1	R9C7[1][A]	u_i2c_slave_top/u_i2c_slave/di_reg_1_s0/Q
4.502	0.548	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/CLK
3.781	0.160	tHld		1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path9

Path Summary:

Slack	0.727
Data Arrival Time	4.502
Data Required Time	3.775
From	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0
To	u_i2c_slave_top/gw_sp
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C6[2][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0/CLK
3.954	0.333	tC2Q	RR	1	R8C6[2][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_4_s0/Q
4.502	0.548	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/AD[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/CLK
3.775	0.154	tHld		1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path10

Path Summary:

Slack	0.727
Data Arrival Time	4.502
Data Required Time	3.775
From	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0
To	u_i2c_slave_top/gw_sp
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C6[2][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0/CLK
3.954	0.333	tC2Q	RR	1	R8C6[2][B]	u_i2c_slave_top/u_i2c_slave/ad_reg_2_s0/Q
4.502	0.548	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/AD[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/CLK
3.775	0.154	tHld		1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path11

Path Summary:

Slack	0.727
Data Arrival Time	4.502
Data Required Time	3.775
From	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0
To	u_i2c_slave_top/gw_sp
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C6[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0/CLK
3.954	0.333	tC2Q	RR	1	R8C6[1][A]	u_i2c_slave_top/u_i2c_slave/ad_reg_0_s0/Q
4.502	0.548	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/AD[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp/CLK
3.775	0.154	tHld		1	BSRAM_R10[0]	u_i2c_slave_top/gw_sp

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.548, 62.168%; tC2Q: 0.333, 37.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path12

Path Summary:

Slack	0.730
Data Arrival Time	4.351
Data Required Time	3.621
From	counter0_2_s0
To	counter0_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C15[1][A]	counter0_2_s0/CLK
3.954	0.333	tC2Q	RR	2	R7C15[1][A]	counter0_2_s0/Q
3.957	0.002	tNET	RR	2	R7C15[1][A]	n35_s/I1
4.351	0.394	tINS	RF	1	R7C15[1][A]	n35_s/SUM
4.351	0.000	tNET	FF	1	R7C15[1][A]	counter0_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C15[1][A]	counter0_2_s0/CLK
3.621	0.000	tHld		1	R7C15[1][A]	counter0_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path13

Path Summary:

Slack	0.730
Data Arrival Time	4.351
Data Required Time	3.621
From	counter0_6_s0
To	counter0_6_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C16[0][A]	counter0_6_s0/CLK
3.954	0.333	tC2Q	RR	2	R7C16[0][A]	counter0_6_s0/Q
3.957	0.002	tNET	RR	2	R7C16[0][A]	n31_s/I1
4.351	0.394	tINS	RF	1	R7C16[0][A]	n31_s/SUM
4.351	0.000	tNET	FF	1	R7C16[0][A]	counter0_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C16[0][A]	counter0_6_s0/CLK
3.621	0.000	tHld		1	R7C16[0][A]	counter0_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path14

Path Summary:

Slack	0.730
Data Arrival Time	4.351
Data Required Time	3.621
From	counter0_8_s0
To	counter0_8_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C16[1][A]	counter0_8_s0/CLK
3.954	0.333	tC2Q	RR	2	R7C16[1][A]	counter0_8_s0/Q
3.957	0.002	tNET	RR	2	R7C16[1][A]	n29_s/I1
4.351	0.394	tINS	RF	1	R7C16[1][A]	n29_s/SUM
4.351	0.000	tNET	FF	1	R7C16[1][A]	counter0_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C16[1][A]	counter0_8_s0/CLK
3.621	0.000	tHld		1	R7C16[1][A]	counter0_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path15

Path Summary:

Slack	0.730
Data Arrival Time	4.351
Data Required Time	3.621
From	counter0_12_s0
To	counter0_12_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C17[0][A]	counter0_12_s0/CLK
3.954	0.333	tC2Q	RR	2	R7C17[0][A]	counter0_12_s0/Q
3.957	0.002	tNET	RR	2	R7C17[0][A]	n25_s/I1
4.351	0.394	tINS	RF	1	R7C17[0][A]	n25_s/SUM
4.351	0.000	tNET	FF	1	R7C17[0][A]	counter0_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C17[0][A]	counter0_12_s0/CLK
3.621	0.000	tHld		1	R7C17[0][A]	counter0_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path16

Path Summary:

Slack	0.730
Data Arrival Time	4.351
Data Required Time	3.621
From	counter0_14_s0
To	counter0_14_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C17[1][A]	counter0_14_s0/CLK
3.954	0.333	tC2Q	RR	2	R7C17[1][A]	counter0_14_s0/Q
3.957	0.002	tNET	RR	2	R7C17[1][A]	n23_s/I1
4.351	0.394	tINS	RF	1	R7C17[1][A]	n23_s/SUM
4.351	0.000	tNET	FF	1	R7C17[1][A]	counter0_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C17[1][A]	counter0_14_s0/CLK
3.621	0.000	tHld		1	R7C17[1][A]	counter0_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path17

Path Summary:

Slack	0.835
Data Arrival Time	4.468
Data Required Time	3.634
From	clk_en_s0
To	delay_rst_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[1][A]	clk_en_s0/CLK
3.954	0.333	tC2Q	RR	6	R9C15[1][A]	clk_en_s0/Q
4.468	0.514	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.634	0.012	tHld		1	R8C15[0][A]	delay_rst_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.514, 60.649%; tC2Q: 0.333, 39.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path18

Path Summary:

Slack	0.835
Data Arrival Time	4.468
Data Required Time	3.634
From	clk_en_s0
To	delay_rst_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[1][A]	clk_en_s0/CLK
3.954	0.333	tC2Q	RR	6	R9C15[1][A]	clk_en_s0/Q
4.468	0.514	tNET	RR	1	R8C15[1][B]	delay_rst_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[1][B]	delay_rst_2_s0/CLK
3.634	0.012	tHld		1	R8C15[1][B]	delay_rst_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.514, 60.649%; tC2Q: 0.333, 39.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path19

Path Summary:

Slack	0.835
Data Arrival Time	4.468
Data Required Time	3.634
From	clk_en_s0
To	delay_rst_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[1][A]	clk_en_s0/CLK
3.954	0.333	tC2Q	RR	6	R9C15[1][A]	clk_en_s0/Q
4.468	0.514	tNET	RR	1	R8C15[0][B]	delay_rst_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][B]	delay_rst_3_s0/CLK
3.634	0.012	tHld		1	R8C15[0][B]	delay_rst_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.514, 60.649%; tC2Q: 0.333, 39.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path20

Path Summary:

Slack	0.835
Data Arrival Time	4.468
Data Required Time	3.634
From	clk_en_s0
To	delay_rst_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[1][A]	clk_en_s0/CLK
3.954	0.333	tC2Q	RR	6	R9C15[1][A]	clk_en_s0/Q
4.468	0.514	tNET	RR	1	R8C15[1][A]	delay_rst_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[1][A]	delay_rst_4_s0/CLK
3.634	0.012	tHld		1	R8C15[1][A]	delay_rst_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.514, 60.649%; tC2Q: 0.333, 39.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path21

Path Summary:

Slack	0.835
Data Arrival Time	4.468
Data Required Time	3.634
From	clk_en_s0
To	delay_rst_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C15[1][A]	clk_en_s0/CLK
3.954	0.333	tC2Q	RR	6	R9C15[1][A]	clk_en_s0/Q
4.468	0.514	tNET	RR	1	R8C15[2][B]	delay_rst_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[2][B]	delay_rst_5_s0/CLK
3.634	0.012	tHld		1	R8C15[2][B]	delay_rst_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.514, 60.649%; tC2Q: 0.333, 39.351%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path22

Path Summary:

Slack	0.853
Data Arrival Time	4.474
Data Required Time	3.621
From	counter0_1_s0
To	counter0_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C15[0][B]	counter0_1_s0/CLK
3.954	0.333	tC2Q	RR	2	R7C15[0][B]	counter0_1_s0/Q
3.957	0.002	tNET	RR	2	R7C15[0][B]	n36_s/I0
4.474	0.517	tINS	RF	1	R7C15[0][B]	n36_s/SUM
4.474	0.000	tNET	FF	1	R7C15[0][B]	counter0_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C15[0][B]	counter0_1_s0/CLK
3.621	0.000	tHld		1	R7C15[0][B]	counter0_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path23

Path Summary:

Slack	0.864
Data Arrival Time	4.498
Data Required Time	3.634
From	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C12[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/CLK
3.954	0.333	tC2Q	RR	16	R9C12[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/Q
4.498	0.543	tNET	RR	1	R9C8[2][A]	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C8[2][A]	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0/CLK
3.634	0.012	tHld		1	R9C8[2][A]	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.543, 61.974%; tC2Q: 0.333, 38.026%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path24

Path Summary:

Slack	0.864
Data Arrival Time	4.498
Data Required Time	3.634
From	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C12[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/CLK
3.954	0.333	tC2Q	RR	16	R9C12[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/Q
4.498	0.543	tNET	RR	1	R9C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0/CLK
3.634	0.012	tHld		1	R9C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.543, 61.974%; tC2Q: 0.333, 38.026%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path25

Path Summary:

Slack	0.864
Data Arrival Time	4.498
Data Required Time	3.634
From	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C12[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/CLK
3.954	0.333	tC2Q	RR	16	R9C12[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_enable_s0/Q
4.498	0.543	tNET	RR	1	R9C8[2][B]	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C8[2][B]	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CLK
3.634	0.012	tHld		1	R9C8[2][B]	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.543, 61.974%; tC2Q: 0.333, 38.026%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	12.840
Data Arrival Time	10.797
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/int_reg_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
10.797	3.592	tNET	FF	1	IOB19[B]	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	IOB19[B]	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CLK
23.637	-0.043	tSu		1	IOB19[B]	u_i2c_slave_top/u_i2c_slave/int_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 8.796%; route: 6.032, 84.763%; tC2Q: 0.458, 6.440%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path2

Path Summary:

Slack	13.478
Data Arrival Time	10.159
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/scl_reg_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
10.159	2.953	tNET	FF	1	IOB12[A]	u_i2c_slave_top/u_i2c_slave/scl_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	IOB12[A]	u_i2c_slave_top/u_i2c_slave/scl_reg_s0/CLK
23.637	-0.043	tSu		1	IOB12[A]	u_i2c_slave_top/u_i2c_slave/scl_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 9.663%; route: 5.394, 83.262%; tC2Q: 0.458, 7.075%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path3

Path Summary:

Slack	13.640
Data Arrival Time	9.997
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/w_r_flag_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.997	2.792	tNET	FF	1	R11C10[0][A]	u_i2c_slave_top/u_i2c_slave/w_r_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C10[0][A]	u_i2c_slave_top/u_i2c_slave/w_r_flag_s0/CLK
23.637	-0.043	tSu		1	R11C10[0][A]	u_i2c_slave_top/u_i2c_slave/w_r_flag_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 9.910%; route: 5.232, 82.834%; tC2Q: 0.458, 7.256%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path4

Path Summary:

Slack	13.798
Data Arrival Time	9.840
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.840	2.634	tNET	FF	1	R8C10[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C10[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CLK
23.637	-0.043	tSu		1	R8C10[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.164%; route: 5.075, 82.395%; tC2Q: 0.458, 7.442%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path5

Path Summary:

Slack	13.798
Data Arrival Time	9.840
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.840	2.634	tNET	FF	1	R8C10[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C10[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_0_s0/CLK
23.637	-0.043	tSu		1	R8C10[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.164%; route: 5.075, 82.395%; tC2Q: 0.458, 7.442%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path6

Path Summary:

Slack	13.809
Data Arrival Time	9.828
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/sda_reg_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.828	2.623	tNET	FF	1	IOB14[A]	u_i2c_slave_top/u_i2c_slave/sda_reg_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	IOB14[A]	u_i2c_slave_top/u_i2c_slave/sda_reg_s0/CLK
23.637	-0.043	tSu		1	IOB14[A]	u_i2c_slave_top/u_i2c_slave/sda_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.183%; route: 5.063, 82.361%; tC2Q: 0.458, 7.456%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path7

Path Summary:

Slack	13.812
Data Arrival Time	9.825
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.825	2.620	tNET	FF	1	R7C10[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R7C10[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CLK
23.637	-0.043	tSu		1	R7C10[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.188%; route: 5.060, 82.353%; tC2Q: 0.458, 7.459%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path8

Path Summary:

Slack	14.115
Data Arrival Time	9.523
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/ack_flag_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.523	2.317	tNET	FF	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLK
23.637	-0.043	tSu		1	R11C12[1][A]	u_i2c_slave_top/u_i2c_slave/ack_flag_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.715%; route: 4.758, 81.439%; tC2Q: 0.458, 7.845%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path9

Path Summary:

Slack	14.115
Data Arrival Time	9.523
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/cstate_0_s1
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.523	2.317	tNET	FF	1	R11C12[2][B]	u_i2c_slave_top/u_i2c_slave/cstate_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C12[2][B]	u_i2c_slave_top/u_i2c_slave/cstate_0_s1/CLK
23.637	-0.043	tSu		1	R11C12[2][B]	u_i2c_slave_top/u_i2c_slave/cstate_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.715%; route: 4.758, 81.439%; tC2Q: 0.458, 7.845%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path10

Path Summary:

Slack	14.129
Data Arrival Time	9.508
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/cstate_3_s1
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.508	2.303	tNET	FF	1	R12C12[0][B]	u_i2c_slave_top/u_i2c_slave/cstate_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R12C12[0][B]	u_i2c_slave_top/u_i2c_slave/cstate_3_s1/CLK
23.637	-0.043	tSu		1	R12C12[0][B]	u_i2c_slave_top/u_i2c_slave/cstate_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.742%; route: 4.743, 81.393%; tC2Q: 0.458, 7.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path11

Path Summary:

Slack	14.134
Data Arrival Time	9.504
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/cstate_2_s1
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.504	2.298	tNET	FF	1	R12C11[0][B]	u_i2c_slave_top/u_i2c_slave/cstate_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R12C11[0][B]	u_i2c_slave_top/u_i2c_slave/cstate_2_s1/CLK
23.637	-0.043	tSu		1	R12C11[0][B]	u_i2c_slave_top/u_i2c_slave/cstate_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 10.750%; route: 4.739, 81.379%; tC2Q: 0.458, 7.871%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path12

Path Summary:

Slack	14.277
Data Arrival Time	9.360
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/word_add_flag_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.360	2.155	tNET	FF	1	R9C8[1][A]	u_i2c_slave_top/u_i2c_slave/word_add_flag_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C8[1][A]	u_i2c_slave_top/u_i2c_slave/word_add_flag_s2/CLK
23.637	-0.043	tSu		1	R9C8[1][A]	u_i2c_slave_top/u_i2c_slave/word_add_flag_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.021%; route: 4.595, 80.909%; tC2Q: 0.458, 8.070%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path13

Path Summary:

Slack	14.277
Data Arrival Time	9.360
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.360	2.155	tNET	FF	1	R9C8[2][A]	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C8[2][A]	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0/CLK
23.637	-0.043	tSu		1	R9C8[2][A]	u_i2c_slave_top/u_i2c_slave/in_reg_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.021%; route: 4.595, 80.909%; tC2Q: 0.458, 8.070%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path14

Path Summary:

Slack	14.277
Data Arrival Time	9.360
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.360	2.155	tNET	FF	1	R9C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0/CLK
23.637	-0.043	tSu		1	R9C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.021%; route: 4.595, 80.909%; tC2Q: 0.458, 8.070%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path15

Path Summary:

Slack	14.277
Data Arrival Time	9.360
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.360	2.155	tNET	FF	1	R9C8[2][B]	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C8[2][B]	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CLK
23.637	-0.043	tSu		1	R9C8[2][B]	u_i2c_slave_top/u_i2c_slave/in_reg_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.021%; route: 4.595, 80.909%; tC2Q: 0.458, 8.070%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path16

Path Summary:

Slack	14.277
Data Arrival Time	9.360
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.360	2.155	tNET	FF	1	R9C8[0][B]	u_i2c_slave_top/u_i2c_slave/in_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C8[0][B]	u_i2c_slave_top/u_i2c_slave/in_reg_5_s0/CLK
23.637	-0.043	tSu		1	R9C8[0][B]	u_i2c_slave_top/u_i2c_slave/in_reg_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.021%; route: 4.595, 80.909%; tC2Q: 0.458, 8.070%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path17

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLK
23.637	-0.043	tSu		1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path18

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R9C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLK
23.637	-0.043	tSu		1	R9C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path19

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLK
23.637	-0.043	tSu		1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path20

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R9C9[2][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C9[2][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0/CLK
23.637	-0.043	tSu		1	R9C9[2][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path21

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLK
23.637	-0.043	tSu		1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path22

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R9C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R9C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLK
23.637	-0.043	tSu		1	R9C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path23

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLK
23.637	-0.043	tSu		1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path24

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLK
23.637	-0.043	tSu		1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path25

Path Summary:

Slack	14.287
Data Arrival Time	9.350
Data Required Time	23.637
From	delay_rst_0_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.680	0.244	tNET	RR	1	IOB8[B]	delay_rst_0_s0/CLK
4.139	0.458	tC2Q	RF	2	IOB8[B]	delay_rst_0_s0/Q
6.579	2.441	tNET	FF	1	R8C15[3][A]	rstn1_s0/I0
7.205	0.626	tINS	FF	54	R8C15[3][A]	rstn1_s0/F
9.350	2.145	tNET	FF	1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
23.680	0.244	tNET	RR	1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLK
23.637	-0.043	tSu		1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 11.041%; route: 4.586, 80.876%; tC2Q: 0.458, 8.083%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.785
Data Arrival Time	5.419
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/scl_negedge_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.419	0.502	tNET	RR	1	R8C14[0][A]	u_i2c_slave_top/u_i2c_slave/scl_negedge_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C14[0][A]	u_i2c_slave_top/u_i2c_slave/scl_negedge_s0/CLK
3.634	0.012	tHld		1	R8C14[0][A]	u_i2c_slave_top/u_i2c_slave/scl_negedge_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 40.273%; route: 0.740, 41.186%; tC2Q: 0.333, 18.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path2

Path Summary:

Slack	1.785
Data Arrival Time	5.419
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/scl_reg_dly_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.419	0.502	tNET	RR	1	R8C14[0][B]	u_i2c_slave_top/u_i2c_slave/scl_reg_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C14[0][B]	u_i2c_slave_top/u_i2c_slave/scl_reg_dly_s0/CLK
3.634	0.012	tHld		1	R8C14[0][B]	u_i2c_slave_top/u_i2c_slave/scl_reg_dly_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 40.273%; route: 0.740, 41.186%; tC2Q: 0.333, 18.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path3

Path Summary:

Slack	2.056
Data Arrival Time	5.690
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.690	0.773	tNET	RR	1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/CLK
3.634	0.012	tHld		1	R7C13[0][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.993%; route: 1.012, 48.896%; tC2Q: 0.333, 16.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path4

Path Summary:

Slack	2.056
Data Arrival Time	5.690
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.690	0.773	tNET	RR	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2/CLK
3.634	0.012	tHld		1	R7C13[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_3_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.993%; route: 1.012, 48.896%; tC2Q: 0.333, 16.111%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path5

Path Summary:

Slack	2.064
Data Arrival Time	5.698
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.698	0.781	tNET	RR	1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/CLK
3.634	0.012	tHld		1	R8C12[2][B]	u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.866%; route: 1.019, 49.081%; tC2Q: 0.333, 16.053%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path6

Path Summary:

Slack	2.085
Data Arrival Time	5.719
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.719	0.802	tNET	RR	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2/CLK
3.634	0.012	tHld		1	R11C13[0][A]	u_i2c_slave_top/u_i2c_slave/slave_addr_flag_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.517%; route: 1.040, 49.592%; tC2Q: 0.333, 15.892%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path7

Path Summary:

Slack	2.093
Data Arrival Time	5.726
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.726	0.809	tNET	RR	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2/CLK
3.634	0.012	tHld		1	R7C12[0][A]	u_i2c_slave_top/u_i2c_slave/bit_counter_2_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.394%; route: 1.048, 49.771%; tC2Q: 0.333, 15.835%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path8

Path Summary:

Slack	2.093
Data Arrival Time	5.726
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/cstate_1_s1
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.726	0.809	tNET	RR	1	R12C13[0][A]	u_i2c_slave_top/u_i2c_slave/cstate_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R12C13[0][A]	u_i2c_slave_top/u_i2c_slave/cstate_1_s1/CLK
3.634	0.012	tHld		1	R12C13[0][A]	u_i2c_slave_top/u_i2c_slave/cstate_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.394%; route: 1.048, 49.771%; tC2Q: 0.333, 15.835%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path9

Path Summary:

Slack	2.093
Data Arrival Time	5.726
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/scl_posedge_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
5.726	0.809	tNET	RR	1	R9C12[1][A]	u_i2c_slave_top/u_i2c_slave/scl_posedge_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C12[1][A]	u_i2c_slave_top/u_i2c_slave/scl_posedge_s0/CLK
3.634	0.012	tHld		1	R9C12[1][A]	u_i2c_slave_top/u_i2c_slave/scl_posedge_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 34.394%; route: 1.048, 49.771%; tC2Q: 0.333, 15.835%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path10

Path Summary:

Slack	2.519
Data Arrival Time	6.152
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/is_write_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.152	1.235	tNET	RR	1	R9C7[0][B]	u_i2c_slave_top/u_i2c_slave/is_write_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C7[0][B]	u_i2c_slave_top/u_i2c_slave/is_write_s0/CLK
3.634	0.012	tHld		1	R9C7[0][B]	u_i2c_slave_top/u_i2c_slave/is_write_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.604%; route: 1.474, 58.226%; tC2Q: 0.333, 13.170%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path11

Path Summary:

Slack	2.519
Data Arrival Time	6.152
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.152	1.235	tNET	RR	1	R7C9[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C9[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/CLK
3.634	0.012	tHld		1	R7C9[1][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.604%; route: 1.474, 58.226%; tC2Q: 0.333, 13.170%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path12

Path Summary:

Slack	2.519
Data Arrival Time	6.152
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.152	1.235	tNET	RR	1	R8C8[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C8[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_1_s0/CLK
3.634	0.012	tHld		1	R8C8[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.604%; route: 1.474, 58.226%; tC2Q: 0.333, 13.170%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path13

Path Summary:

Slack	2.519
Data Arrival Time	6.152
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_6_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.152	1.235	tNET	RR	1	R7C8[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C8[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_6_s0/CLK
3.634	0.012	tHld		1	R7C8[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.604%; route: 1.474, 58.226%; tC2Q: 0.333, 13.170%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path14

Path Summary:

Slack	2.519
Data Arrival Time	6.152
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/in_reg_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.152	1.235	tNET	RR	1	R11C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_0_s0/CLK
3.634	0.012	tHld		1	R11C8[0][A]	u_i2c_slave_top/u_i2c_slave/in_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.604%; route: 1.474, 58.226%; tC2Q: 0.333, 13.170%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path15

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0/CLK
3.634	0.012	tHld		1	R11C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path16

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R9C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLK
3.634	0.012	tHld		1	R9C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path17

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0/CLK
3.634	0.012	tHld		1	R11C9[1][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path18

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R9C9[2][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C9[2][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0/CLK
3.634	0.012	tHld		1	R9C9[2][A]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path19

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLK
3.634	0.012	tHld		1	R8C9[0][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path20

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R9C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R9C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLK
3.634	0.012	tHld		1	R9C9[2][B]	u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path21

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_2_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0/CLK
3.634	0.012	tHld		1	R11C7[2][B]	u_i2c_slave_top/u_i2c_slave/word_address_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path22

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_3_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0/CLK
3.634	0.012	tHld		1	R11C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path23

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_4_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0/CLK
3.634	0.012	tHld		1	R8C7[0][B]	u_i2c_slave_top/u_i2c_slave/word_address_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path24

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_5_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R7C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R7C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_5_s0/CLK
3.634	0.012	tHld		1	R7C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path25

Path Summary:

Slack	2.525
Data Arrival Time	6.158
Data Required Time	3.634
From	delay_rst_1_s0
To	u_i2c_slave_top/u_i2c_slave/word_address_7_s0
Launch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	your_instance_name/pll_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C15[0][A]	delay_rst_1_s0/CLK
3.954	0.333	tC2Q	RF	2	R8C15[0][A]	delay_rst_1_s0/Q
4.193	0.238	tNET	FF	1	R8C15[3][A]	rstn1_s0/I1
4.917	0.724	tINS	FR	54	R8C15[3][A]	rstn1_s0/F
6.158	1.242	tNET	RR	1	R8C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					your_instance_name/pll_inst/CLKOUT.default_gen_clk
3.437	3.437	tCL	RR	113	PLL_L	your_instance_name/pll_inst/CLKOUT
3.621	0.185	tNET	RR	1	R8C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s0/CLK
3.634	0.012	tHld		1	R8C7[2][A]	u_i2c_slave_top/u_i2c_slave/word_address_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay	cell: 0.724, 28.534%; route: 1.480, 58.328%; tC2Q: 0.333, 13.137%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	counter0_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	counter0_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	counter0_14_s0/CLK

MPW2

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	counter0_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	counter0_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	counter0_12_s0/CLK

MPW3

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	counter0_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	counter0_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	counter0_8_s0/CLK

MPW4

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	counter0_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	counter0_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	counter0_0_s0/CLK

MPW5

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	u_i2c_slave_top/u_i2c_slave/sp_out_reg_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	u_i2c_slave_top/u_i2c_slave/sp_out_reg_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	u_i2c_slave_top/u_i2c_slave/sp_out_reg_1_s0/CLK

MPW6

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/CLK

MPW7

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	u_i2c_slave_top/u_i2c_slave/addr_len_reg_8_s0/CLK

MPW8

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	u_i2c_slave_top/u_i2c_slave/sp_out_reg_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	u_i2c_slave_top/u_i2c_slave/sp_out_reg_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	u_i2c_slave_top/u_i2c_slave/sp_out_reg_2_s0/CLK

MPW9

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	u_i2c_slave_top/u_i2c_slave/int_reg_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	u_i2c_slave_top/u_i2c_slave/int_reg_s0/CLK

MPW10

MPW Summary:

Slack:	8.672
Actual Width:	9.922
Required Width:	1.250
Type:	Low Pulse Width
Clock:	your_instance_name/pll_inst/CLKOUT.default_gen_clk
Objects:	u_i2c_slave_top/u_i2c_slave/word_address_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
13.437	3.437	tCL	FF	your_instance_name/pll_inst/CLKOUT
13.699	0.262	tNET	FF	u_i2c_slave_top/u_i2c_slave/word_address_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			your_instance_name/pll_inst/CLKOUT.default_gen_clk
23.437	3.437	tCL	RR	your_instance_name/pll_inst/CLKOUT
23.621	0.185	tNET	RR	u_i2c_slave_top/u_i2c_slave/word_address_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
113	clkout_50m	9.103	0.262
54	rstn1	10.888	3.592
33	w_r_flag	11.595	1.836
19	n1037_12	9.103	1.338
17	n20_3	14.690	1.452
16	in_reg_enable	9.367	1.505
16	n635_12	11.494	1.341
15	bit_counter[0]	10.582	1.352
15	bit_counter[3]	10.851	1.006
14	n1938_4	10.582	1.338

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R7C16	81.94%
R9C8	79.17%
R11C2	79.17%
R9C10	76.39%
R8C6	73.61%
R8C15	66.67%
R7C15	65.28%
R9C7	63.89%
R9C12	62.50%
R8C10	58.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name CLK_50M -period 20 -waveform {0 10} [get_ports {clk_50m}]
TC_GENERATED_CLOCK	Invalid	create_generated_clock -name CLKOUT_50M -source [get_ports {clk_50m}] -master_clock CLK_50M [get_nets {clkout_50m}]