PnR Messages

Report Title PnR Report
Design File E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\impl\gwsynthesis\gw_i2c_slave.vg
Physical Constraints File E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\i2c_slave.cst
Timing Constraints File E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\gw_i2c_slave.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-LV4LQ144C6/I5
Device GW1N-4
Created Time Tue Sep 24 15:03:45 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.016s, Elapsed time = 0h 0m 0.015s Placement Phase 1: CPU time = 0h 0m 0.059s, Elapsed time = 0h 0m 0.06s Placement Phase 2: CPU time = 0h 0m 0.019s, Elapsed time = 0h 0m 0.019s Placement Phase 3: CPU time = 0h 0m 0.778s, Elapsed time = 0h 0m 0.778s Total Placement: CPU time = 0h 0m 0.872s, Elapsed time = 0h 0m 0.872s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.041s, Elapsed time = 0h 0m 0.041s Routing Phase 2: CPU time = 0h 0m 0.105s, Elapsed time = 0h 0m 0.105s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.146s, Elapsed time = 0h 0m 0.146s Generate output files: CPU time = 0h 0m 0.574s, Elapsed time = 0h 0m 0.574s
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 220MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 210/4608 5%
    --LUT,ALU,ROM16 210(194 LUT, 16 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 112/3756 3%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 108/3456 4%
    --I/O Register as Latch 0/300 0%
    --I/O Register as FF 4/300 2%
CLS 144/2304 7%
I/O Port 7/120 6%
I/O Buf 7 -
    --Input Buf 3 -
    --Output Buf 3 -
    --Inout Buf 1 -
BSRAM 1 SP
 10%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/330%
bank 1 0/240%
bank 2 6/3815%
bank 3 1/254%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 0/8 0%
GCLK_PIN 0/6 0%

Global Clock Signals:

Signal Global Clock Location
clk_50m_d PRIMARY LEFT
clkout_50m PRIMARY LEFT

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk_50m - 6/3 Y in IOL3[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
rst_n - 43/2 Y in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
scl_pull - 49/2 Y out IOB12[B] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
sda_pull - 51/2 Y out IOB14[B] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
int_o - 57/2 Y out IOB19[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
scl - 48/2 Y io IOB12[A] LVCMOS33 NA NONE ON NONE NA NA NA NA 3.3
sda - 50/2 Y io IOB14[A] LVCMOS33 8 NONE NA NONE OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
144/0 - in IOT2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
143/0 - in IOT3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
142/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
141/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
140/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
139/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
138/0 - in IOT7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
137/0 - in IOT7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
136/0 - in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
135/0 - in IOT9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
134/0 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
133/0 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
132/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
131/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
130/0 - in IOT16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
129/0 - in IOT16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
128/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
126/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
124/0 - in IOT20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
123/0 - in IOT22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
122/0 - in IOT22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
121/0 - in IOT24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
120/0 - in IOT24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
119/0 - in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
118/0 - in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
117/0 - in IOT30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
116/0 - in IOT30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
115/0 - in IOT33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
114/0 - in IOT33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
113/0 - in IOT35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
112/0 - in IOT35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
111/0 - in IOT37[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
110/0 - in IOT37[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
34/2 - in IOB5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
38/2 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
39/2 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
40/2 - in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
41/2 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
42/2 - in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
43/2 rst_n in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
44/2 - in IOB10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
45/2 - in IOB10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
46/2 - in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
47/2 - in IOB11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
48/2 scl in IOB12[A] LVCMOS33 NA NONE ON NONE NA NA NA NA 3.3
49/2 scl_pull out IOB12[B] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
50/2 sda io IOB14[A] LVCMOS33 8 NONE NA NONE OFF NA NA NA 3.3
51/2 sda_pull out IOB14[B] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
52/2 - in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
54/2 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
56/2 - in IOB19[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
57/2 int_o out IOB19[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
58/2 - in IOB20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
59/2 - in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
60/2 - in IOB21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
61/2 - in IOB21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
62/2 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
63/2 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
64/2 - in IOB24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
65/2 - in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
66/2 - in IOB26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
67/2 - in IOB26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
68/2 - in IOB28[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
69/2 - in IOB28[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
70/2 - in IOB30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
71/2 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
75/2 - in IOB34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
72/2 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
78/2 - in IOB36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
76/2 - in IOB36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
3/3 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
4/3 - in IOL3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
6/3 clk_50m in IOL3[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
7/3 - in IOL4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
8/3 - in IOL4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
9/3 - in IOL6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
10/3 - in IOL6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
11/3 - in IOL9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
12/3 - in IOL9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
13/3 - in IOL10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
14/3 - in IOL10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
15/3 - in IOL10[C] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
16/3 - in IOL10[D] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
18/3 - out IOL10[E] LVCMOS18 8 UP NA NA OFF NA NA NA 1.2
20/3 - in IOL10[F] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
21/3 - in IOL10[G] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
22/3 - in IOL10[H] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
23/3 - in IOL10[I] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
24/3 - in IOL10[J] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
25/3 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
26/3 - in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
27/3 - in IOL13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
28/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
29/3 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
30/3 - in IOL15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
106/1 - in IOR3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
104/1 - in IOR3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
102/1 - in IOR4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
101/1 - in IOR4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
100/1 - in IOR6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
99/1 - in IOR6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
98/1 - in IOR9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
97/1 - in IOR9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
96/1 - in IOR10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
95/1 - in IOR10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
94/1 - in IOR10[C] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
93/1 - in IOR10[D] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
92/1 - in IOR10[E] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
90/1 - in IOR10[F] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
88/1 - in IOR10[G] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/1 - in IOR10[H] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/1 - in IOR10[I] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/1 - in IOR10[J] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/1 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/1 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/1 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8