Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\i2c_slave_defines.v E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\I2C_SLAVE_TOP.v E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\rom_init.v E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\gw_i2c_slave.v E:\work_files\IP_A_new\work_2024\I2C\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\gowin_pll\gowin_pll.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-LV4LQ144C6/I5 |
| Device | GW1N-4 |
| Created Time | Tue Sep 24 15:03:43 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | gw_i2c_slave |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 215.613MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 215.613MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 215.613MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 215.613MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 215.613MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 215.613MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 215.613MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 215.613MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 215.613MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 215.613MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 215.613MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 215.613MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 215.613MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 215.613MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 215.613MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 7 |
| I/O Buf | 7 |
| IBUF | 3 |
| OBUF | 3 |
| IOBUF | 1 |
| Register | 103 |
| DFF | 3 |
| DFFE | 34 |
| DFFR | 19 |
| DFFP | 4 |
| DFFC | 8 |
| DFFCE | 35 |
| LUT | 182 |
| LUT2 | 15 |
| LUT3 | 54 |
| LUT4 | 113 |
| ALU | 15 |
| ALU | 15 |
| INV | 3 |
| INV | 3 |
| BSRAM | 1 |
| SP | 1 |
| CLOCK | 1 |
| PLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 200(185 LUT, 15 ALU) / 4608 | 5% |
| Register | 103 / 3756 | 3% |
| --Register as Latch | 0 / 3756 | 0% |
| --Register as FF | 103 / 3756 | 3% |
| BSRAM | 1 / 10 | 10% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_50m | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_50m_ibuf/I | ||
| 2 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk_50m_ibuf/I | clk_50m | your_instance_name/pll_inst/CLKOUT |
| 3 | your_instance_name/pll_inst/CLKOUTP.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk_50m_ibuf/I | clk_50m | your_instance_name/pll_inst/CLKOUTP |
| 4 | your_instance_name/pll_inst/CLKOUTD.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | clk_50m_ibuf/I | clk_50m | your_instance_name/pll_inst/CLKOUTD |
| 5 | your_instance_name/pll_inst/CLKOUTD3.default_gen_clk | Generated | 60.000 | 16.7 | 0.000 | 30.000 | clk_50m_ibuf/I | clk_50m | your_instance_name/pll_inst/CLKOUTD3 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | 50.000(MHz) | 100.127(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 10.013 |
| Data Arrival Time | 11.469 |
| Data Required Time | 21.482 |
| From | u_i2c_slave_top/u_i2c_slave/scl_posedge_s0 |
| To | u_i2c_slave_top/u_i2c_slave/ack_flag_s2 |
| Launch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/scl_posedge_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 14 | u_i2c_slave_top/u_i2c_slave/scl_posedge_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n2061_s5/I1 |
| 4.399 | 1.099 | tINS | FF | 3 | u_i2c_slave_top/u_i2c_slave/n2061_s5/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1938_s3/I1 |
| 6.458 | 1.099 | tINS | FF | 2 | u_i2c_slave_top/u_i2c_slave/n1938_s3/F |
| 7.418 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1025_s20/I1 |
| 8.517 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1025_s20/F |
| 9.477 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1025_s19/I0 |
| 10.509 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1025_s19/F |
| 11.469 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/ack_flag_s2/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 21.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 21.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/ack_flag_s2/CLK |
| 21.482 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/ack_flag_s2 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 11.402 |
| Data Required Time | 21.482 |
| From | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0 |
| To | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0 |
| Launch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 4 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n638_s4/I1 |
| 4.399 | 1.099 | tINS | FF | 3 | u_i2c_slave_top/u_i2c_slave/n638_s4/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n637_s5/I1 |
| 6.458 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n637_s5/F |
| 7.418 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n637_s3/I0 |
| 8.450 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n637_s3/F |
| 9.410 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n637_s2/I0 |
| 10.442 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n637_s2/F |
| 11.402 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 21.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 21.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLK |
| 21.482 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 11.402 |
| Data Required Time | 21.482 |
| From | u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2 |
| To | u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0 |
| Launch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/CLK |
| 2.340 | 0.458 | tC2Q | RF | 13 | u_i2c_slave_top/u_i2c_slave/bit_counter_1_s2/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n2061_s4/I1 |
| 4.399 | 1.099 | tINS | FF | 5 | u_i2c_slave_top/u_i2c_slave/n2061_s4/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n635_s8/I0 |
| 6.391 | 1.032 | tINS | FF | 16 | u_i2c_slave_top/u_i2c_slave/n635_s8/F |
| 7.351 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n636_s3/I1 |
| 8.450 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n636_s3/F |
| 9.410 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n636_s2/I0 |
| 10.442 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n636_s2/F |
| 11.402 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 21.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 21.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0/CLK |
| 21.482 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 11.402 |
| Data Required Time | 21.482 |
| From | u_i2c_slave_top/u_i2c_slave/in_reg_4_s0 |
| To | u_i2c_slave_top/u_i2c_slave/cstate_1_s1 |
| Launch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 5 | u_i2c_slave_top/u_i2c_slave/in_reg_4_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1938_s4/I1 |
| 4.399 | 1.099 | tINS | FF | 2 | u_i2c_slave_top/u_i2c_slave/n1938_s4/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1041_s15/I0 |
| 6.391 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1041_s15/F |
| 7.351 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1041_s9/I0 |
| 8.383 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1041_s9/F |
| 9.343 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1041_s7/I1 |
| 10.442 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1041_s7/F |
| 11.402 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/cstate_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 21.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 21.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/cstate_1_s1/CLK |
| 21.482 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/cstate_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | 10.223 |
| Data Arrival Time | 11.259 |
| Data Required Time | 21.482 |
| From | u_i2c_slave_top/u_i2c_slave/start_condition_s0 |
| To | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2 |
| Launch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | your_instance_name/pll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 1.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 1.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/start_condition_s0/CLK |
| 2.340 | 0.458 | tC2Q | RF | 5 | u_i2c_slave_top/u_i2c_slave/start_condition_s0/Q |
| 3.300 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1037_s8/I1 |
| 4.399 | 1.099 | tINS | FF | 19 | u_i2c_slave_top/u_i2c_slave/n1037_s8/F |
| 5.359 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1029_s32/I1 |
| 6.458 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1029_s32/F |
| 7.418 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1029_s30/I1 |
| 8.517 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1029_s30/F |
| 9.477 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1029_s29/I2 |
| 10.299 | 0.822 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1029_s29/F |
| 11.259 | 0.960 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | your_instance_name/pll_inst/CLKOUT.default_gen_clk | |||
| 21.156 | 1.156 | tCL | RR | 104 | your_instance_name/pll_inst/CLKOUT |
| 21.882 | 0.726 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2/CLK |
| 21.482 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s2 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.119, 43.925%; route: 4.800, 51.187%; tC2Q: 0.458, 4.888% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |