Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\IP release\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_Release_210918\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\gw_i2c_slave.v D:\IP release\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_Release_210918\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\I2C_SLAVE_TOP.v D:\IP release\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_Release_210918\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\rom_init.v D:\IP release\i2c_sram\Gowin_I2C_Master_Slave_refDesign_For_Release_210918\Gowin_I2C_Slave_refDesign\gw_i2c_slave\src\gowin_rpll\gowin_rpll.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Version | GowinSynthesis V1.9.8.01 |
| Part Number | GW1N-LV4LQ144C6/I5 |
| Device | GW1N-4 |
| Created Time | Wed Sep 22 15:49:20 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | gw_i2c_slave |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.171s, Peak memory usage = 192.344MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 192.344MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 192.344MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 192.344MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 192.344MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 192.344MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 192.344MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 192.344MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 192.344MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 192.344MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 192.344MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 192.344MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 192.344MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 192.344MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 192.344MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 7 |
| I/O Buf | 7 |
| IBUF | 3 |
| OBUF | 3 |
| IOBUF | 1 |
| Register | 103 |
| DFF | 3 |
| DFFE | 38 |
| DFFR | 19 |
| DFFP | 4 |
| DFFC | 8 |
| DFFCE | 31 |
| LUT | 175 |
| LUT2 | 14 |
| LUT3 | 56 |
| LUT4 | 105 |
| ALU | 15 |
| ALU | 15 |
| INV | 3 |
| INV | 3 |
| BSRAM | 1 |
| SP | 1 |
| CLOCK | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 193(178 LUTs, 15 ALUs) / 4608 | 4% |
| Register | 103 / 3756 | 3% |
| --Register as Latch | 0 / 3756 | 0% |
| --Register as FF | 103 / 3756 | 3% |
| BSRAM | 1 / 10 | 10% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk_50m | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_50m_ibuf/I | ||
| u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk_50m_ibuf/I | clk_50m | u_Gowin_rPLL/rpll_inst/CLKOUT |
| u_Gowin_rPLL/rpll_inst/CLKOUTP.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | clk_50m_ibuf/I | clk_50m | u_Gowin_rPLL/rpll_inst/CLKOUTP |
| u_Gowin_rPLL/rpll_inst/CLKOUTD.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | clk_50m_ibuf/I | clk_50m | u_Gowin_rPLL/rpll_inst/CLKOUTD |
| u_Gowin_rPLL/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 60.000 | 16.7 | 0.000 | 30.000 | clk_50m_ibuf/I | clk_50m | u_Gowin_rPLL/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | 50.0(MHz) | 131.8(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 12.413 |
| Data Arrival Time | 9.308 |
| Data Required Time | 21.721 |
| From | u_i2c_slave_top/u_i2c_slave/bit_counter_2_s0 |
| To | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s0 |
| Launch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 1.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 2.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_2_s0/CLK |
| 2.579 | 0.458 | tC2Q | RF | 6 | u_i2c_slave_top/u_i2c_slave/bit_counter_2_s0/Q |
| 3.059 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1056_s23/I1 |
| 4.158 | 1.099 | tINS | FF | 7 | u_i2c_slave_top/u_i2c_slave/n1056_s23/F |
| 4.638 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_3_s10/I1 |
| 5.737 | 1.099 | tINS | FF | 2 | u_i2c_slave_top/u_i2c_slave/bit_counter_3_s10/F |
| 6.217 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1060_s35/I0 |
| 7.249 | 1.032 | tINS | FF | 3 | u_i2c_slave_top/u_i2c_slave/n1060_s35/F |
| 7.729 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1064_s34/I1 |
| 8.828 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1064_s34/F |
| 9.308 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 21.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 22.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s0/CLK |
| 21.721 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 2
Path Summary:| Slack | 12.413 |
| Data Arrival Time | 9.308 |
| Data Required Time | 21.721 |
| From | u_i2c_slave_top/u_i2c_slave/bit_counter_1_s0 |
| To | u_i2c_slave_top/u_i2c_slave/clken_s0 |
| Launch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 1.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 2.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/bit_counter_1_s0/CLK |
| 2.579 | 0.458 | tC2Q | RF | 8 | u_i2c_slave_top/u_i2c_slave/bit_counter_1_s0/Q |
| 3.059 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1058_s36/I1 |
| 4.158 | 1.099 | tINS | FF | 5 | u_i2c_slave_top/u_i2c_slave/n1058_s36/F |
| 4.638 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/word_address_7_s5/I1 |
| 5.737 | 1.099 | tINS | FF | 3 | u_i2c_slave_top/u_i2c_slave/word_address_7_s5/F |
| 6.217 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1045_s16/I1 |
| 7.316 | 1.099 | tINS | FF | 2 | u_i2c_slave_top/u_i2c_slave/n1045_s16/F |
| 7.796 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1045_s15/I0 |
| 8.828 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n1045_s15/F |
| 9.308 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/clken_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 21.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 22.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/clken_s0/CLK |
| 21.721 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/clken_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 3
Path Summary:| Slack | 12.413 |
| Data Arrival Time | 9.308 |
| Data Required Time | 21.721 |
| From | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0 |
| To | u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0 |
| Launch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 1.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 2.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLK |
| 2.579 | 0.458 | tC2Q | RF | 5 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/Q |
| 3.059 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n654_s7/I1 |
| 4.158 | 1.099 | tINS | FF | 5 | u_i2c_slave_top/u_i2c_slave/n654_s7/F |
| 4.638 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n658_s5/I1 |
| 5.737 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n658_s5/F |
| 6.217 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n658_s3/I1 |
| 7.316 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n658_s3/F |
| 7.796 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n658_s7/I0 |
| 8.828 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n658_s7/F |
| 9.308 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 21.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 22.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0/CLK |
| 21.721 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 4
Path Summary:| Slack | 12.413 |
| Data Arrival Time | 9.308 |
| Data Required Time | 21.721 |
| From | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0 |
| To | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0 |
| Launch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 1.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 2.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLK |
| 2.579 | 0.458 | tC2Q | RF | 5 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/Q |
| 3.059 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n654_s7/I1 |
| 4.158 | 1.099 | tINS | FF | 5 | u_i2c_slave_top/u_i2c_slave/n654_s7/F |
| 4.638 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n657_s5/I1 |
| 5.737 | 1.099 | tINS | FF | 2 | u_i2c_slave_top/u_i2c_slave/n657_s5/F |
| 6.217 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n657_s4/I0 |
| 7.249 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n657_s4/F |
| 7.729 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n657_s6/I1 |
| 8.828 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n657_s6/F |
| 9.308 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 21.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 22.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0/CLK |
| 21.721 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
Path 5
Path Summary:| Slack | 12.413 |
| Data Arrival Time | 9.308 |
| Data Required Time | 21.721 |
| From | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0 |
| To | u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0 |
| Launch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 1.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 2.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/CLK |
| 2.579 | 0.458 | tC2Q | RF | 5 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_1_s0/Q |
| 3.059 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n654_s7/I1 |
| 4.158 | 1.099 | tINS | FF | 5 | u_i2c_slave_top/u_i2c_slave/n654_s7/F |
| 4.638 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n654_s6/I1 |
| 5.737 | 1.099 | tINS | FF | 3 | u_i2c_slave_top/u_i2c_slave/n654_s6/F |
| 6.217 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n655_s4/I0 |
| 7.249 | 1.032 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n655_s4/F |
| 7.729 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/n655_s7/I1 |
| 8.828 | 1.099 | tINS | FF | 1 | u_i2c_slave_top/u_i2c_slave/n655_s7/F |
| 9.308 | 0.480 | tNET | FF | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_rPLL/rpll_inst/CLKOUT.default_gen_clk | |||
| 21.758 | 1.758 | tCL | RR | 104 | u_Gowin_rPLL/rpll_inst/CLKOUT |
| 22.121 | 0.363 | tNET | RR | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0/CLK |
| 21.721 | -0.400 | tSu | 1 | u_i2c_slave_top/u_i2c_slave/addr_len_reg_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.363, 100.000% |