Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDR1\data\ddr_code.v D:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDR1\data\DDR1_TOP.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2AR-LV18LQ176C8/I7 |
| Device | GW2AR-18 |
| Created Time | Wed Jun 29 09:50:39 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDR_Memory_Interface_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.998s, Elapsed time = 0h 0m 1s, Peak memory usage = 68.320MB Running netlist conversion: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 68.320MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 68.320MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.131s, Peak memory usage = 68.320MB Optimizing Phase 2: CPU time = 0h 0m 0.374s, Elapsed time = 0h 0m 0.381s, Peak memory usage = 68.320MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.182s, Peak memory usage = 68.320MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 68.320MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 68.320MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 68.320MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.235s, Peak memory usage = 68.320MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.322s, Peak memory usage = 68.320MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 68.320MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 84.145MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.327s, Elapsed time = 0h 0m 0.36s, Peak memory usage = 84.145MB Generate output files: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 84.145MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 84.145MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 182 |
| Embedded Port | 41 |
| I/O Buf | 213 |
| IBUF | 99 |
| OBUF | 96 |
| IOBUF | 18 |
| Register | 1270 |
| DFF | 145 |
| DFFE | 138 |
| DFFSE | 26 |
| DFFR | 1 |
| DFFRE | 38 |
| DFFP | 47 |
| DFFPE | 4 |
| DFFC | 611 |
| DFFCE | 260 |
| LUT | 1154 |
| LUT2 | 274 |
| LUT3 | 320 |
| LUT4 | 560 |
| ALU | 82 |
| ALU | 82 |
| SSRAM | 72 |
| RAM16S4 | 6 |
| RAM16SDP4 | 66 |
| INV | 16 |
| INV | 16 |
| IOLOGIC | 92 |
| ODDR | 19 |
| IDES4_MEM | 16 |
| OSER4 | 2 |
| OSER4_MEM | 18 |
| IODELAY | 37 |
| CLOCK | 4 |
| CLKDIV | 1 |
| DQS | 2 |
| DQCE | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1684(1170 LUTs, 82 ALUs, 72 SSRAMs) / 20736 | 8% |
| Register | 1270 / 16095 | 8% |
| --Register as Latch | 0 / 16095 | 0% |
| --Register as FF | 1270 / 16095 | 8% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| memory_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | memory_clk_ibuf/I | ||
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I | ||
| u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 20.000 | 50.0 | 0.000 | 10.000 | memory_clk_ibuf/I | memory_clk | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | memory_clk | 100.0(MHz) | 1364.3(MHz) | 1 | TOP |
| 2 | clk | 100.0(MHz) | 250.4(MHz) | 6 | TOP |
| 3 | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 50.0(MHz) | 152.3(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.496 |
| Data Arrival Time | 5.329 |
| Data Required Time | 5.826 |
| From | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0 |
| To | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 1362 | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 7 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.PRE_ALL_CMD_WAIT_s23/I1 |
| 1.375 | 0.555 | tINS | FF | 8 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.PRE_ALL_CMD_WAIT_s23/F |
| 1.612 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s25/I2 |
| 2.065 | 0.453 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s25/F |
| 2.302 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/I2 |
| 2.755 | 0.453 | tINS | FF | 4 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/F |
| 2.992 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s1/I0 |
| 3.509 | 0.517 | tINS | FF | 8 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s1/F |
| 3.746 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s0/I1 |
| 4.300 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s0/F |
| 4.537 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/I1 |
| 5.092 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
| 5.329 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.924 | 0.237 | tNET | FF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKIN |
| 6.110 | 0.186 | tINS | FF | 40 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
| 6.347 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.313 | -0.035 | tUnc | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.826 | -0.487 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.997 |
| Setup Relationship: | 5.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | 0.496 |
| Data Arrival Time | 5.329 |
| Data Required Time | 5.826 |
| From | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0 |
| To | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Launch Clk | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F] |
| Latch Clk | memory_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 1362 | u_gw_phy_mc_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 7 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/timer_cnt_7_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.PRE_ALL_CMD_WAIT_s23/I1 |
| 1.375 | 0.555 | tINS | FF | 8 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/init_next_state.PRE_ALL_CMD_WAIT_s23/F |
| 1.612 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s25/I2 |
| 2.065 | 0.453 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s25/F |
| 2.302 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/I2 |
| 2.755 | 0.453 | tINS | FF | 4 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/read_cal_next_state.READ_CAL_WRITE_CMD_s17/F |
| 2.992 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s1/I0 |
| 3.509 | 0.517 | tINS | FF | 8 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s1/F |
| 3.746 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s0/I1 |
| 4.300 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/n1630_s0/F |
| 4.537 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/I1 |
| 5.092 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_init/hold_Z_s/F |
| 5.329 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 5.000 | 0.000 | memory_clk | |||
| 5.000 | 0.000 | tCL | FF | 1 | memory_clk_ibuf/I |
| 5.688 | 0.688 | tINS | FF | 1 | memory_clk_ibuf/O |
| 5.924 | 0.237 | tNET | FF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKIN |
| 6.110 | 0.186 | tINS | FF | 40 | u_gw_phy_mc_top/u_ddr_phy_top/u_dqce_clk_x2/CLKOUT |
| 6.347 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK |
| 6.313 | -0.035 | tUnc | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs | ||
| 5.826 | -0.487 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/u_ddr_phy_wd/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs |
| Clock Skew: | 0.997 |
| Setup Relationship: | 5.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:| Slack | 6.006 |
| Data Arrival Time | 4.822 |
| Data Required Time | 10.828 |
| From | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
| To | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_0_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 38 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/I1 |
| 1.887 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/I2 |
| 2.577 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/F |
| 2.814 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s3/I3 |
| 3.185 | 0.371 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s3/F |
| 3.422 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s2/I3 |
| 3.793 | 0.371 | tINS | FF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s2/F |
| 4.030 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s1/I1 |
| 4.585 | 0.555 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s1/F |
| 4.822 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 38 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_0_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.305, 58.222%; route: 1.422, 35.918%; tC2Q: 0.232, 5.860% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.026 |
| Data Arrival Time | 4.802 |
| Data Required Time | 10.828 |
| From | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
| To | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 38 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/I1 |
| 1.887 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/I2 |
| 2.577 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/F |
| 2.814 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s15/I2 |
| 3.267 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s15/F |
| 3.504 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s13/I2 |
| 3.957 | 0.453 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s13/F |
| 4.194 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s12/I3 |
| 4.565 | 0.371 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_0_s12/F |
| 4.802 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 38 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.285, 58.009%; route: 1.422, 36.101%; tC2Q: 0.232, 5.890% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.108 |
| Data Arrival Time | 4.720 |
| Data Required Time | 10.828 |
| From | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0 |
| To | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_1_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 38 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/I1 |
| 1.887 | 0.555 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/flag_d_0_s15/F |
| 2.124 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/I2 |
| 2.577 | 0.453 | tINS | FF | 2 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/ns_memsync_2_s17/F |
| 2.814 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s3/I3 |
| 3.185 | 0.371 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s3/F |
| 3.422 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s2/I3 |
| 3.793 | 0.371 | tINS | FF | 3 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n295_s2/F |
| 4.030 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n294_s1/I2 |
| 4.483 | 0.453 | tINS | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/n294_s1/F |
| 4.720 | 0.237 | tNET | FF | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 38 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_1_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_gw_phy_mc_top/u_ddr_phy_top/ddr_sync/count_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.203, 57.117%; route: 1.422, 36.868%; tC2Q: 0.232, 6.015% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |