The Arora GW1AN series packs serious capability into a small‑FPGA footprint, delivering standout efficiency and performance for cost‑sensitive designs. With upgraded packaging, hardened IP subsystems, and integrated user flash supporting background programming and multi‑image reliability, the 1AN family brings big‑system features into compact devices.

Enhanced ADC performance, plus pin‑compatibility with competitor devices, makes it easy to drop into existing designs or build robust dual‑source strategies without compromise.

All of this comes in one of the lowest‑cost FPGA families on the market—making GW1AN the ideal choice for high‑volume, space‑constrained, budget‑critical applications.

Arora I FPGA Product Features

Low Power Operation

• 1.2 V core voltage support
• Dynamic clock gating for reduced power consumption

Integrated Non‑Volatile Memory

• On‑chip 4 Mbit NOR Flash for configuration and user storage

Comprehensive I/O Standard Support

• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL 3.3
• SSTL 3.3/2.5/1.8 (Class I & II), SSTL15
• HSTL 1.8 (Class I & II), HSTL15
• PCI, LVDS25, LVDS25E, RSDS, BLVDSE, MLVDSE, LVPECLE, RSDSE
• Input hysteresis options
• Adjustable drive strength
• Bus‑keeper, pull‑up/down, and open‑drain options
• Hot‑socketing supported

Logic Resources

• Efficient LUT4‑based logic fabric
• Built‑in support for shift‑register implementations

Memory Blocks

• Block SRAM with multiple operating modes:
• Dual‑Port, Single‑Port, Semi‑Dual‑Port

Flexible Clocking

• Configurable PLLs including output phase adjustment
• Global clock networks

Configuration Options (Package dependant)

• JTAG, AUTO‑BOOT, SSPI, MSPI, SERIAL, CPU