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DK_START_GW1NSE-UX2CLQ144C5I4_V3.1

Previous Name: DK-START-GW1NSE2

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Features

  • Lower power consumption
    • 55nm embedded flash technology
    • Core voltage: 2V
    • GW1NSE-2C supports LX and UX
    • GW1NSE-4C supports LV
    • Clock dynamically turns on and off
  • Hard core processor
    • Cortex-M3 32-bit RISC
    • ARM3v7M architecture optimized for small-footprint embedded applications
    • System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
    • Thumb compatible Thumb-2-only instruction set processor core for high code density
    • GW1NSE-2C supports up to 30 MHz operating frequency
    • GW1NSE-4C supports up to 80 MHz operating frequency
    • Hardware-division and single-cycle-multiplication
    • Integrated nested vectored interrupt controller (NVIC) providing deterministic interrupt handling
    • 26 interrupts with eight priority levels
    • Memory protection unit (MPU), providing a privileged mode for protecting operation system functionality
    • Unaligned data access, enabling data to be efficiently packed into memory
    • Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
    • Timer0 and Timer1
    • UART0 and UART1
    • Watchdog
    • Debug port: JTAG and TPIU
  • Provides OTP Authentication code
  • USB2.0 PHY
    • 480Mbps data speed, compatible with USB1.1 1.5/12Mbps data speed
    • Plug and play
    • Hot socket
  • ADC
    • Eight channels
    • 12-bit SAR AD conversion
    • Slew Rate: 1MHz
    • Dynamic range: >81 dB SFDR,>62 db SINAD
    • Linear performance: INL<1 LSB, DNL<0.5 LSB, no missing codes
  • User Flash
    • 128K Byte storage space embedded in GW1NSE-2C
    • 32K Byte storage space embedded in GW1NSE-4C
    • 32-bit data width
  • Provide a Root of Trust based on SRAM PUF technology
  • Multiple I/O Standards
    • LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE
    • MLVDSE, LVPECLE, RSDSE
    • Input hysteresis option
    • Supports 4mA,8mA,16mA,24mA,etc. drive options
    • Slew Rate option
    • Output drive strength option
    • Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option
    • Hot Socket
    • BANK0 supports MIPI input
    • BANK2 supports MIPI output
    • BANK0 and BANK2 support I3C
  • Abundant Slices
    • Four input LUT (LUT4)
    • Double-edge flip-flops
    • Supports shifter register
  • Block SRAM with multiple modes
    • Supports Dual Port, Single Port, and Semi Dual Port
    • Supports bytes write enable
  • Flexible PLLs
    • Frequency adjustment (multiply and division) and phase adjustment
    • Supports global clock
  • Built-in Flash programming
    • Instant-on
    • Supports security bit operation
    • Supports AUTO BOOT and DUAL BOOT
  • Configuration
    • JTAG configuration
    • Supports on-chip DUAL BOOT configuration mode
    • Multiple GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL

 

Documents Download
User Guide DK-START-GW1NSE2 Development Board Quick Start User Guide Download
Data Sheet GW1NSE series of SecureFPGA Products Datasheet** Download