Evaluating GW5AT SerDes Channel Performance Across Various Transmission Media   1 Abstract   This white paper presents the performance evaluation of the GW5AT SerDes (Serializer/Deserializer) solution under different channel configurations and cable assemblies. The tests aim to assess the signal integrity and achievable data rates across a variety of interconnect media, including standard PCB, ISI boards, DisplayPort (DP) cables, HDMI cables, HSD cables, and fiber optics.   2 Introduction   As high-speed serial interfaces continue to evolve, ensuring robust data transmission across various physical channels becomes increasingly important. Testing GW5AT’s SerDes (Serializer/Deserializer) technology across different transport media—such as various types of cables (e.g., coaxial, twisted pair, optical fiber) is important for several critical reasons: Signal Integrity Varies with Cable Type Different cables introduce different types of signal degradation: Attenuation (loss of signal strength) Crosstalk (interference between channels) Impedance mismatch and reflections Dispersion (especially in fiber) SerDes systems must maintain low bit error rates (BER) even under these degradations.   Cable Length and Material Affect Performance Longer cables increase latency and attenuation. Material differences (e.g., copper vs. fiber) affect signal speed, bandwidth, and electromagnetic interference (EMI). SerDes systems must be tested for maximum reach and data integrity across realistic distances.   Jitter and Timing Recovery Depend on Media Jitter tolerance (timing variation) is a key parameter in SerDes design. Different media introduce different jitter profiles, which impact clock and data recovery (CDR) circuits.   EMC/EMI Compliance and Robustness Cable shielding and construction affect electromagnetic compatibility. Testing ensures the SerDes link does not emit or succumb to unacceptable EMI, especially in industrial or automotive applications.   Application-Specific Reliability Applications (data center, automotive, aerospace) use different media due to environmental, cost, or legacy reasons. SerDes must be tested for real-world deployment scenarios: e.g., harsh environments in automotive vs. controlled data center conditions.   Standard Compliance Industry standards (e.g., PCIe, Ethernet, JESD204B/C) specify performance over certain types of media. Testing across those media ensures compliance and interoperability.   Equalization and Adaptive Algorithms Tuning SerDes often use adaptive equalization to compensate for channel loss. Testing across different media helps tune these algorithms for best performance under various conditions.   In Summary, testing SerDes technology with different transport media is essential to validate performance, reliability, compliance, and interoperability. Without this, the system may fail or underperform in actual deployment environments.   3 Basic Terminologies   Let’s review some basic concepts and terminologies before going into the detailed discussion of the testing and results.   3.1 Channel Insertion Loss Channel Insertion Loss is the loss of signal power that occurs as the signal travels through a transmission channel (such as a cable, PCB trace, connector, or backplane).It tells you how much signal is lost between the transmitter and receiver at a given frequency. Insertion Loss (IL) is the ratio (in dB) of the signal power at the input vs. the signal power at the output of a transmission path, often expressed as a function of frequency. Formula:   Insertion loss is caused by a combination of: Factor Description Conductor Resistance Causes I²R losses (especially at high frequencies due to skin effect) Dielectric Losses Energy lost in the insulation material of the cable or PCB Radiation/EMI Losses Some energy escapes as electromagnetic radiation Connector/Discontinuity Losses Caused by impedance mismatches and physical breaks in the channel   Typical behavior with Frequency as follows Insertion loss increases with frequency. At high data rates (e.g., 10+ Gbps), even small lengths of PCB trace or cable can introduce significant attenuation. Measured typically using a Vector Network Analyzer (VNA) or Time Domain Reflectometer (TDR).    Here is an example of the Channel Insertion Loss curve, showing how signal loss increases with frequency. As you can see, higher frequencies (common in high-speed SerDes systems) experience significantly greater attenuation, which is why insertion loss is a critical parameter to evaluate and compensate for in system design.   In our actual test system, the total insertion loss represents the attenuation from the serializer SIO pin to the Deserializer SIO pin and includes several components. Each IL of components is measured as follows:   Serializer PKG & PCB Trace: -2 dB Deserializer PKG & PCB Trace: -2 dB Cable Assembly Insertion Loss: Cable A & C: -0.5 dB each ISI Board or Cable B: varies by configuration     3.2 Emphasis Technology   Emphasis technology refers to signal conditioning techniques that shape the transmitted waveform by adjusting the amplitude of different signal parts, which are usually based on transition patterns, to counteract channel losses. It’s commonly used in high-speed serial links like PCIe, USB, Ethernet, SATA, etc., to maintain data integrity over lossy media (e.g., long cables, backplanes, PCB traces).   There are mainly two types of Emphasis technology. Both techniques boost high-frequency content (which tends to get attenuated more on real channels) but do so in different ways.   Pre-Emphasis: Increases the amplitude of signal transitions (i.e., when the bit changes from 0→1 or 1→0) De-Emphasis: Decreases the amplitude of steady-state signals (i.e., when the bit stays the same over time)   3.3 PRBS Signals   A PRBS (Pseudo-Random Binary Sequence) is a deterministic, repeatable sequence of binary bits (0 and 1) that mimics the randomness of real-world data traffic but is generated using a known mathematical formula. It's called “pseudo-random” because the sequence appears random, but it’s generated by a fixed pattern from a shift register with feedback taps. Common PRBS Patterns PRBS Pattern Sequence Length Use Case PRBS-7 127 bits General SerDes or USB 3.0 PRBS-9 511 bits SATA, DisplayPort PRBS-15 32,767 bits Moderate stress test PRBS-23 8.3 million bits Longer memory/channel tests PRBS-31 ~2.1 billion bits High-stress, long-term testing (Ethernet, 100G+)   PRBS is often used in Serdes testing for: Transmitter compliance testing (e.g., measuring eye diagram or jitter) Receiver sensitivity testing Loopback tests (internal or external) BER tests: PRBS is sent, then checked for mismatches at the receiver     3.4 BER Testing   BER (Bit Error Rate) is the ratio of the number of bit errors to the total number of bits transmitted during a test.   Example: If 10 errors occur over 1,000,000,000 bits:   BER testing is the process of transmitting a known data pattern (like a PRBS sequence) through the communication channel and comparing the received data to the original. Any mismatches are counted as bit errors. The goal of BER testing is as follows:   Goal Why it matters Verify Link Reliability Ensure low BER over time (e.g., 1e-12 or lower) Compliance Testing Required by standards (PCIe, USB, Ethernet, etc.) Evaluate Equalization/Emphasis See how well TX/RX equalizers recover data Compare Media Performance Measure how different cables or PCBs affect BER Test Clock/Data Recovery (CDR) Ensure stable data recovery in receiver   Here is a simulated BER vs. Time plot for a high-speed link test:   The green curve shows how BER improves over time as the link stabilizes. The red dashed line marks a common industry target BER threshold of 1e-12. In a real test, this helps verify if the system meets reliability specs over time.   4 Test Setup   To ensure accurate cable measurement results, a series of carefully designed testing steps are followed. Since the test setup requires additional boards and cables to connect the cable under test, these supporting components must be measured first to account for their impact. The detailed setup of the test bench is described in the following sections. 4.1 Hardware Configuration The first step is to measure the transmitter character with the tester and its probe cables. The following diagram shows the detailed setup. Test Setup 1: TX Performance Observation   The transmitter board is EVAL_GW5AT_60KUG225_V1’s LN1 TX connector, and the receiver board is EVAL_GW5AT_60KUG225_V1’s LN1 RX connector. Here is the actual picture of this setup: Test Setup 1   The second step is to measure the ISI board characters as the following diagram: Setup 2: ISI board connected to the Tx and Rx boards   The following shows the actual setup picture:   ISI board connections The 3rd step is to measure the actual target cable performance. The test bench was set up as described as follows:   Test Setup 3: Cable Assemblies     4.2 Common Test Parameters Here are some common test parameters used in the tests we just described in the last section.   Bit Error Rate (BER) Target: 1e-12 Test Pattern: PRBS15 TX De-emphasis: Varied (-1.94 dB to -6 dB) RX Equalization: AUTO Cable Lengths: Ranged from 0.3m to 10m, depending on media   4.3 Test Equipment Here is the test equipment list we used in the tests we described previously:   Oscilloscope: Keysight UXR0254A Network Analyzer: Keysight E5071C   4.4 Channel Insertion Loss Here are the insertion loss represents the attenuation from the serializer SIO pin to the Deserializer SIO pin, and includes:   Serializer PKG & PCB Trace: -2 dB Deserializer PKG & PCB Trace: -2 dB Cable Assembly Insertion Loss: Cable A & C: -0.5 dB each ISI Board or Cable B: varies by configuration 5 Test Results with Different Channels   5.1       TX Performance   The first test is to observe the transmitter characteristics. The following picture shows the test setup. The board that is used here is EVAL_GW5AT_60KUG225_V1. All the cables will be used in the following test steps.   Test setup for Transmit performance observation   The Eye Diagrams observed for different speeds are as follows: Eye Diagram at 12.5Gbps Eye Diagram at 10Gbps   5.2       FR4 ISI Board   The second test is to observe the ISI board‘s characteristics. The following picture shows the test setup. The board that is used here is the ISI board. All the cables will be used in the following test steps.   ISI board testing setup   Here are the channel loss measurement results for the 0.635-meter PCB trace and 0.3-meter PCB trace on the ISI board:   Channel loss measurement results   For speed testing, we monitor the internal Serdes data received through our proprietary FPGA testing channels. The failure point is indicated by the total collapse of the eye diagram.  The following internal eye diagram is for a 0.635m FR4 PCB trace, the signal is running at 9Gbps. The transmitter side De-emphasis is set at -6 dB.     Internal Eye diagram The following internal eye diagram is for a 0.3m FR4 PCB trace, the signal is running at 12Gbps. The transmitter side De-emphasis is set at -6 dB.   Internal Eye diagram   5.3      DP 1.4 Cable Measurement The following test is for a DisplayPort 1.4 cable. We chose this cable from the vendor samzheglobal.com. 30 American Wire Gauge (AWG). Cable length is 2 meters. The insertion loss is measured in the following picture: Insertion loss for SAMZHE 30AWG DP cable   The test bench setup is shown in the following picture: Test Setup for DP 1.4 cable measurement   The following internal eye diagram is for a 2m DisplayPort 1.4 cable, the signal is running at 11Gbps. The transmitter side De-emphasis is set at -3 dB.                            Internal Eye diagram   5.4       HDMI 2.1 Cable The following test is for an HDMI 2.1 cable. We chose this cable from vendor UGREEN. 32 AWG. Cable length is 2meters. The insertion loss is measured as the following picture:   Insertion loss for UGREEN 32AWG HDMI cable   The test bench setup is shown in the following picture:   Test Setup for HDMI 2.1 cable measurement   The following internal eye diagram is for a 2m HDMI 2.1 cable, the signal is running at 10Gbps. The transmitter side De-emphasis is set at -3 dB.   Internal Eye diagram   5.5       HSD Cable (Single-Ended Connection) The following test is for HSD cable. 2 cables with lengths of 3 meters and 8 meters are tested. The insertion loss is measured as shown in the following pictures: Sdd21：HSD Cable: 3 m (RG316) insertion loss   Sdd21 HSD Cable: 8 m (RG316) insertion loss   The test bench setup is shown in the following picture:   The following left-side internal eye diagram is for a 3m HSD cable, the signal is running at 8Gbps. The transmitter side De-emphasis is set at -1.94 dB.     The right-side internal eye diagram is for an 8m HSD cable, the signal is running at 6Gbps. The transmitter side De-emphasis is set at -1.94 dB.   5.6 Fiber Optic Cable   The last test is for the optical cable. The cable is SFP-FC16G-SW-CSC, shown in the following picture. It is 10meters long. The internal eye diagram shows that the signal can run at 12Gbps. The transmitter side De-emphasis is set at -1.94 dB. Please note that on this test, the performance can be influenced by the electrical interfaces of the optical module.   6 Summary and Conclusion    The results demonstrate that the GW5AT SerDes channel performance is more sensitive to insertion loss than raw cable length. Among the tested configurations: The ISI board setup yielded the highest performance (up to 12 Gbps). Fiber optics offered comparable performance with superior length capability. HDMI and HSD cables showed lower maximum data rates, limited by signal integrity constraints at extended lengths. Cable quality, gauge, and interconnect interfaces play a critical role in high-speed serial transmission performance. Here is the table that summarizes the test results for the cables measured: cable type cable length（m） Max data rate (Gbps) DP 2 11 HDMI 2 10 HSD(RG316) 8 6 3 8 ISI board（FR4） 0.3 12 0.635 9 fiber optic 10 12 This evaluation provides a foundational reference for system designers choosing appropriate transmission media for applications involving GW5AT SerDes technology.     Support and Feedback GOWIN Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail：support@gowinsemi.com Revision History Date Version Description 2025/08/01 1.0E Initial draft    

Solving TDC Challenges with GOWIN FPGAs: Accurate, Scalable, and Cost-Effective Timing Solutions   1 Abstract   As time-domain applications continue to grow across sectors like 3D sensing, quantum optics, medical imaging, and LiDAR, the demand for high-resolution, scalable, and reliable Time-to-Digital Converter (TDC) solutions has surged. While FPGAs are a popular platform for TDC implementation, traditional approaches often suffer from inconsistent delay lines, environmental sensitivity, and limited channel scalability. This white paper introduces GOWIN Semiconductor’s innovative TDC architecture that leverages dedicated delay lines embedded in FPGA IO blocks. By circumventing the limitations of general-purpose logic fabric, GOWIN FPGAs offer superior timing precision, enhanced thermal and voltage stability, and support for high-density, multi-channel designs. The paper also explores real-world applications, including 3D Time-of-Flight cameras, digital oscilloscopes, and quantum photon counting systems, and demonstrates how GOWIN’s solution reduces cost and power while improving performance. Additionally, the paper presents a unique case study of a DIY Time-Based ADC, showcasing how GOWIN FPGAs enable creative, low-cost, high-resolution signal digitization. For engineers seeking accurate, efficient, and scalable TDC implementation, GOWIN’s FPGA-based solution sets a new standard in time-domain signal processing. 2 Introduction to TOF and TDC technology    Time-of-Flight (ToF)   In the age of smart devices, autonomous systems, and immersive reality, the ability to perceive depth with speed and precision has become essential. At the heart of many advanced sensing solutions lies Time-of-Flight (ToF) technology—an optical distance measurement technique that is revolutionizing fields from mobile photography to robotics and industrial automation. Time-of-Flight is a method for measuring distance by calculating the time it takes for a signal—typically a light pulse or modulated wave—to travel from a source to a target and back. By capturing this "flight time," the system can determine the exact distance to an object. The fundamental principle is simple, but its implementation relies on cutting-edge optoelectronics and timing technologies. A typical ToF system consists of: Light Source: Often a VCSEL (Vertical-Cavity Surface-Emitting Laser) that emits near-infrared light. Sensor: Usually a SPAD (Single-Photon Avalanche Diode) or CMOS sensor that detects returning photons.   Timing Circuitry: Includes a Time-to-Digital Converter (TDC) that measures the time delay with extreme precision. Concept of ToF from Wikipedia   There are two main types of ToF systems. One is Direct ToF (dToF). It measures the actual time delay between the emitted and received pulse. The other one is Indirect ToF (iToF). It measures the phase shift of a modulated light signal to estimate distance.   There are several Key Advantages of ToF. Real-time 3D Mapping: Generates depth maps at video frame rates. Compact & Low Power: Especially iToF, which is ideal for smartphones and AR glasses. High Accuracy & Range: Direct ToF can achieve centimeter to millimeter-level accuracy even over long distances. Versatile Integration: Easily embedded in consumer, automotive, and industrial systems.   As technology continues to evolve, ToF sensors are becoming smaller, faster, and more accurate. Future innovations will likely combine ToF with AI, edge computing, and multi-modal sensing (e.g., combining ToF with RGB or thermal imaging) to enable smarter, context-aware devices.   Time-to-Digital Converter (TDC)   A Time-to-Digital Converter (TDC) is an electronic circuit that measures the time interval between two events and converts it into a digital number. Unlike traditional ADCs (Analog-to-Digital Converters) that digitize voltage levels, TDCs focus on timing precision, offering exceptional performance for time-domain applications.   TDCs are essential in: Time-of-Flight (ToF) systems Particle detectors Optical communication LiDAR and 3D imaging Medical scanners (PET, CT) High-resolution oscilloscopes   TDCs measure the time between a start and stop signal. Depending on the architecture, they can achieve resolutions from nanoseconds down to tens of picoseconds or even lower.   Common Architectures: Delay Line TDC: Uses a chain of logic gates or buffers with known delay. Captures which stage the signal reaches when stopped. Simple and fast, but limited in resolution and sensitive to process/temperature. Vernier TDC: Uses two delay lines with slightly different delays. The difference is used to interpolate timing more precisely. Higher resolution but more complex. Ring Oscillator or Counter-based TDC: Measures coarse time with a counter and fine time with a delay chain. Offers a wide dynamic range and scalable performance. Time Interleaving or Multi-phase Clock: Improves throughput by parallelizing the measurement process. Ideal for high-frequency, high-event-rate applications.     Schematic of TDC based on Vernier Deley Line   Many TDCs are implemented on-chip FPGA or ASIC for flexibility and reduced cost.   3 Implementing TDC in FPGA   Why Use FPGAs for TDC? FPGAs (Field-Programmable Gate Arrays) are ideal for implementing TDCs due to: High-speed internal logic and fine-grained delay elements Parallelism for multi-channel timing Customizability for application-specific requirements Lower cost and faster prototyping compared to ASICs FPGAs enable rapid development of TDCs for applications such as: Time-of-Flight sensors (e.g., LiDAR) Scientific instrumentation (e.g., photon timing, nuclear detectors) Communication systems (e.g., jitter measurement, time synchronization) Common TDC Implementation Techniques in FPGA Tapped Delay Line (TDL) with LUTs and Carry Chains Uses the FPGA’s carry-chain logic as a fine-grained delay line. A signal propagates through the chain; a fast sampling flip-flop array captures the position of the rising edge. The pattern of flip-flop outputs gives a “thermometer code” that’s translated to fine time.  Pros: Simple, high resolution (20–50 ps typically)             Cons: Sensitive to temperature, voltage, and placement variability Vernier Delay Line (VDL) Uses two delay chains with slightly different delays to create a “beat frequency” and interpolate time. Often implemented with carefully tuned LUTs or logic blocks. Pros: Higher resolution than TDL (sub-10 ps achievable) Cons: More complex, calibration-intensive Multiphase Clocking Leverages a PLL to generate multiple clock phases. Uses these clocks to sample the timing signal more finely than the system clock. Pros: Easy to implement, deterministic  Cons: Limited number of phases, coarse resolution (unless combined with other techniques)   One Example of Carry Chain based TDC   Limitations of FPGA-based TDC   Challenge Description Non-uniform delays Delay lines vary due to routing, logic placement, process variation Temperature/voltage drift Delay elements are sensitive to environmental changes Metastability Occurs when sampling fast-changing signals asynchronously Jitter Internal and external clock noise can limit accuracy   4 GOWIN TDC Solution    While implementing TDCs in FPGAs offers tremendous flexibility and performance, designers often face a set of persistent challenges tied to the nature of traditional FPGA fabric. Gowin Semiconductor addresses these issues with a unique architectural innovation, offering a more robust and scalable TDC solution. The Challenges of FPGA-Based TDCs While FPGAs are widely used for implementing TDCs, several technical limitations can impact timing accuracy and reliability: Routing and Placement Variability Traditional TDC designs in FPGAs rely on a general-purpose logic fabric and internal routing. As a result: Delay lines are non-uniform due to synthesis and routing differences. Fine-tuning the layout requires manual floorplanning and careful timing analysis. Achieving consistent results across devices and designs can be difficult. Environmental Sensitivity Standard FPGA delay elements are sensitive to: Temperature changes Voltage fluctuations Process variations This leads to timing drift and requires active calibration or thermal compensation, increasing complexity and design time. Gowin’s Solution: Dedicated IO-Based Delay Architecture To overcome these limitations, Gowin FPGAs integrate dedicated delay lines and registers directly into the IO blocks offering a new standard in accuracy and robustness for TDC design. Key Advantages Stable and Uniform Delay Lines Dedicated delay elements in the IOs are physically consistent and isolated from logic fabric. No dependency on random logic placement or FPGA routing. Ensures high linearity and repeatable measurements across multiple devices and temperature ranges. Reduced Environmental Sensitivity IO block architecture minimizes the impact of process, voltage, and temperature (PVT) variations. Significantly improves timing stability without requiring external calibration or complex compensation logic. High Channel Density Gowin FPGAs offer a high number of IOs per device, enabling the implementation of multi-channel TDCs at low cost. Ideal for applications such as LiDAR, SPAD arrays, and quantum experiments where many parallel timing channels are required. Low-Cost and Power-Efficient By moving the TDC function to dedicated IO resources, Gowin avoids overloading core logic, allowing for smaller and more power-efficient FPGA configurations. Enables system designers to reduce BOM cost while maintaining high performance. Benchmarks 8 bits TDC in GW1N-1K, resolution can be 30ps or less 16 bits TDC in GW1N-2K works well @ 960MHz (7.8cm TDC) 32 bits in GW5A-138K tested @1650MHz (4.54cm TDC) 16 bits in GW5A-138K tested @1600MHz (4.69cm TDC) Note, the clock frequency is the CLK in IOLogic driven by PLL. The resolution X C = distance, where C is the speed of light   Summary While traditional FPGA-based TDCs offer flexibility, they often fall short in terms of consistency, environmental stability, and scalability. Gowin’s dedicated IO-based delay architecture directly addresses these challenges, delivering a stable, accurate, and scalable TDC platform. By combining high IO count, reduced sensitivity to environmental variation, and low cost, Gowin FPGAs offer a differentiated solution for multi-channel TDC implementations—empowering designers to build faster, more reliable time-domain systems with confidence. 5 Device and IP Support  GOWIN TDC solution can be implemented in all Gowin FPGAs. The resolution will vary depending on the devices. Gowin EDA tools provide TDC IP and Guideline documents to help users to implement this solution. Please see IPUG1208-1.0E_Gowin TDC IP User Guide. Here is the EDA software view of this IP:   Here is the IP core generator view:   6 Real World Applications    3D Time-of-Flight (ToF) Cameras ▸ Use Case: ToF cameras are used in mobile devices, industrial automation, gesture control, and augmented reality systems. They emit a short light pulse (typically from a VCSEL) and measure the time it takes for light to bounce off an object and return to the sensor. ▸ Role of FPGA TDC: Each SPAD (Single Photon Avalanche Diode) pixel in a ToF image sensor detects individual photons. A TDC in the FPGA measures the arrival time of the first photon per pulse. Timing precision of 20–100 ps enables accurate depth resolution (down to millimeter scale). Multiple TDCs may run in parallel (one per pixel or pixel group) to support high-resolution, real-time depth maps. ▸ Why FPGA: FPGAs provide massive parallelism, essential for capturing data from hundreds or thousands of SPADs simultaneously. They also allow real-time histogramming and digital filtering, minimizing external processing and improving accuracy. Quantum Optics & Time-Correlated Photon Counting (TCSPC) ▸ Use Case: In quantum communication, quantum key distribution (QKD), and fluorescence lifetime imaging (FLIM), precise photon arrival time is critical. Researchers use these systems to study entanglement, photon correlations, and lifetimes at the single-photon level. ▸ Role of FPGA TDC: TDCs capture photon arrival timestamps with picosecond precision. Used in Time-Correlated Single Photon Counting (TCSPC) to build statistical histograms of photon events over time. Events are often random and sparse, requiring high-resolution, high-sensitivity, low-dead-time timing logic. ▸ Why FPGA: FPGA-based TDCs can be deeply customized for trigger logic, filtering, gating, and correlation algorithms. Researchers often use multi-channel TDCs to correlate events across different detectors. FPGA implementation offers real-time processing, eliminating the need for bulky post-processing steps. Digital Oscilloscopes and Signal Analysis ▸ Use Case: Modern oscilloscopes (especially digital sampling scopes and time interval analyzers) rely on high-precision time capture to measure jitter, edge timing, and propagation delays in high-speed circuits and communication interfaces. ▸ Role of FPGA TDC: TDCs measure time intervals between fast rising/falling edges far more precisely than typical clocked sampling (which is limited to ~200ps at 5 GHz). TDCs can enable interpolation between sample points, enhancing effective timing resolution. Used for jitter analysis, eye diagram generation, and signal integrity testing. ▸ Why FPGA: FPGA fabric is ideal for implementing custom trigger logic, cross-domain synchronization, and time-tagging systems with minimal latency. In portable or embedded scopes, TDCs in FPGAs can reduce BOM cost while still achieving professional-grade accuracy. Precision LiDAR Systems ▸ Use Case: In autonomous vehicles, drones, and surveying systems, LiDAR (Light Detection and Ranging) is used to build real-time 3D maps of the environment. Precision timing is key to converting photon return time into accurate distance. ▸ Role of FPGA TDC: Each laser pulse reflected off an object is captured by a detector (e.g., SPAD or APD). The TDC measures the time from laser emission to photon return. Timing resolution directly impacts ranging accuracy: e.g., 10 ps resolution ≈ 1.5 mm distance accuracy. ▸ Why FPGA: LiDAR often requires multi-beam systems with multiple detectors firing rapidly (up to millions of events per second). FPGA TDCs allow scalable parallelism and on-the-fly filtering to reject noise, ambient light, and invalid events. TDCs implemented in IOs (as in Gowin FPGAs) reduce latency and power, critical for embedded mobile LiDAR. A reconstructed 3D model by using 128-channel TDCs in the GW5A-138K device   7 A DIY Project Example   You can indeed build an ADC (Analog-to-Digital Converter) using TDC (Time-to-Digital Converter) principles. This method is often called a Time-Based ADC or Time-Encoding ADC, and it leverages the conversion of an analog voltage into a time interval, which is then measured by a TDC. Here’s how it works, how it's constructed, and where it's useful: Basic Idea: Instead of directly digitizing voltage levels (as in a traditional ADC), you convert the analog voltage into a time delay, and then measure that delay using a Time-to-Digital Converter. Voltage → Time → Digital This approach takes advantage of the high timing resolution of modern TDCs, often enabling very fine quantization steps with lower power and simpler analog front ends.     How It Works: Core Components Voltage-to-Time Converter (VTC) This circuit converts the analog input voltage into a time delay. Common implementations: Ramp Generator + Comparator: A reference voltage ramps linearly. When it crosses the input voltage, a comparator triggers the stop signal. The time from start of ramp to trigger = analog voltage. Current-Starved Delay Chain: Delay elements modulated by analog voltage control current (and therefore delay). Used in some VCO-based architecture. Time-to-Digital Converter (TDC) Once the analog voltage is converted into a delay (a time interval), a high-resolution TDC digitizes that time. The output is a digital code corresponding to the original input voltage. Timing Diagram (Conceptual): Timing Diagram of ADC based on TDC   ADC Performance Overview Reference implementation and performance validation were conducted on the TANG Nano 4K development board (Chip: GW1NSR-LV4CQN48PC7/I6). Testing Setup:     Results Resolution: 7-bit Sample Rate: 60 kSPS to 1 MSPS Linearity (INL): ±6 LSB @ 60 kSPS ±10 LSB @ 1 MSPS (1 LSB = 10 mV) Input Range: 0–0.8 V Effective Resolution: ~6.5 bits FPGA Resource Utilization (Per ADC Channel) Logic Registers: 160 Block SRAM (BSRAM): 1 block IDES8: 1 unit PLL: 1 LVDS Differential Pair: 1 Single-Ended I/O: 1 This makes the solution efficient for integration into small, cost-sensitive FPGAs while preserving sufficient logic and memory for additional system logic or control tasks Advantages High Resolution: TDCs can achieve ps-level resolution, translating to high-bit ADCs without expensive analog components. Low Power: Especially in applications that need low sampling rates (e.g., instrumentation). Digital-Friendly: Most of the system is digital, making it ideal for FPGA or ASIC implementation. Challenges Nonlinearity: VTCs (especially ramp generators) often suffer from nonlinearity and temperature drift. Calibration: Requires runtime or startup calibration to maintain accuracy. Speed Limitations: Faster input conversion needs faster ramp/delay control, which becomes challenging. Noise Sensitivity: Analog front-end still needs a careful design to reduce jitter and drift. Applications Low-speed, high-resolution sensors (e.g., temperature, pressure, bio-sensing) Time-domain signal processing FPGA-based instrumentation Neuromorphic or event-based processing Radiation-hardened or simplified ADC designs for harsh environments   8 Conclusion    Time-to-Digital Converters are at the heart of many emerging technologies, from high-resolution 3D imaging and LiDAR to quantum research and precision instrumentation. While FPGAs have long been a flexible platform for TDC design, traditional implementations often face limitations in timing accuracy, environmental stability, and scalability.   GOWIN Semiconductor addresses these challenges with a novel IO-based TDC architecture, delivering consistent and precise delay lines that are inherently less sensitive to temperature, voltage, and process variations. This architecture not only improves measurement linearity and timing resolution but also enables high channel density and efficient power utilization, critical for modern applications that demand real-time performance and compact form factors.   By integrating TDC functionality into dedicated IO resources, GOWIN FPGAs simplify design complexity, reduce calibration overhead, and lower total system cost. The result is a scalable, robust, and cost-effective timing solution ideal for engineers and system designers pushing the boundaries of time-domain performance.   As the need for precise timing grows across industries, GOWIN’s FPGA-based TDC solution provides a reliable foundation for innovation, empowering next-generation systems with the accuracy, flexibility, and efficiency required to meet tomorrow’s demands.   Support and Feedback GOWIN Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail：support@gowinsemi.com Revision History Date Version Description 2025/07/08 1.0E Initial draft  

Affordable, Robust, and Fast: GOWIN’s Industrial Gigabit LVDS Networking Solution   1 Abstract   In the era of Industry 4.0, reliable, low-latency communication is crucial for modern industrial systems, yet the high cost and complexity of existing industrial Ethernet solutions remain significant barriers, particularly for small and medium enterprises. This white paper introduces GOWIN Semiconductor’s Gigabit LVDS Datalink with Embedded Clock, a simplified, cost-effective alternative to traditional networking approaches.   Leveraging GOWIN’s EasyCDR® technology and FPGA-embedded resources, this solution supports high-speed, low-power, and deterministic data transmission ideal for PLC backplanes, EtherCAT® slave expansion, energy management systems, and robotic control. The paper outlines the technical architecture, packet protocol, and implementation examples in master/slave configurations, showcasing how GOWIN’s solution reduces wiring complexity, boosts throughput, and enhances noise immunity.   Targeting up to 64 nodes with support for gigabit data rates and integrated CRC and 8b/10b encoding, this scalable solution empowers engineers to build robust, flexible, and efficient industrial networks with minimal overhead.   2 Industry networking solution overview Networking is essential today in industrial control systems because it enables seamless communication, coordination, and efficiency in complex manufacturing environments.   Networks in industry automation    Here are just a few examples: Industrial Automation PLC Control Systems: Serves as an expansion unit for PLCs, connecting sensors and actuators. DCS Systems: Collects and outputs a large number of field signals for process control. Production Line Monitoring: Used for equipment status monitoring and product quality inspection. Building Automation Lighting Control Systems: Digital I/O modules for switch control. HVAC Systems: Interfaces for temperature and humidity sensors. Security Systems: Signal processing for access control and surveillance. Energy Management Power Monitoring Systems: Acquisition of voltage and current signals. New Energy Systems: Interfaces for photovoltaic inverters and wind power converters. Smart Grids: Remote terminal units (RTUs) for monitoring and control. Transportation Rail Transit Signaling Systems Intelligent Traffic Light Control Vehicle Detection and Control Systems Test and Measurement Systems Laboratory Data Acquisition Systems Automated Product Testing Platforms Environmental Monitoring Equipment   Addressing Limitations of Current Industry Network Solutions While current Industrial Ethernet solutions offer advanced capabilities for industrial automation and control systems, enabling real-time control, synchronization, and data exchange, there is still room to improve for even wider spread adoption. The primary barriers are the high costs of hardware, specialized switches, coupled with the complexity of integrating these systems into existing setups, managing latency, and ensuring cybersecurity. These factors limited them to many manufacturers, especially small to medium enterprises.   GOWIN Semiconductor Corp. proposes a simpler, low-cost industrial networking solutions that address these issues effectively. Our solution leverages GOWIN EasyCDR® technology with optimized communication protocols to achieve reliable, low-latency communication suitable for industrial automation production lines, smart factories, energy monitoring systems, and multi-axis robots. By simplifying network configuration, this approach lowers implementation costs and complexity while maintaining essential performance and latency, scalable architecture. This innovative solution could democratize advanced automation networking, making it accessible to a broader range of industries.   3 System Architecture   Network Topology One typical industry network is Sliced IO module on a backplane. The picture below is one example of PLC Module. A Modular Sliced IO system   The following diagram shows the network topology by using the backplane implementation as an example.     As the above diagram shows, the data links (the blue traces) forms a ring topology in the backplane. It includes 2 data stream links between the line cards with an FPGA on it and the wrap around at the end points. The number of line cards can be placed on the backplane, theoretically only limited by the size of the plane; however, the latency of data going through all the line cards will increase with more cards in place.    Though the topology is natural for each line card, this can be implemented with one of these cards as the Master card, while all the others as Slave cards. Beside this backplane example, cabling can also be support with this solution. There will be difference speed that can be achieved with different table and length. In general, we expect typically we can achieve Gigabit per second on 3-meter-long SATA or USB types of cables; 100MHz running on Twist wires CAT5 or CAT6 cables.   Electrical Signaling Backplane systems are critical infrastructure in data centers, telecom switches, industrial control systems, and military applications. These systems demand reliable, high-speed data transmission with minimal noise and low power. Low-Voltage Differential Signaling (LVDS) is a widely adopted interface standard that meets these stringent demands effectively.   High-Speed Performance LVDS supports data transmission rates exceeding 1–3 Gbps per channel, making it suitable for high-throughput applications. Combined with serialization techniques, it can aggregate multiple data channels over fewer lines, reducing routing complexity.   Low Power Operation One of LVDS's hallmark benefits is its low power consumption. The typical voltage swing of ~350 mV results in minimal current drawing, reducing overall system power and enabling dense, thermally efficient designs—an important factor in rack-mounted systems.   Excellent Noise Immunity Differential signaling provides inherent resistance to common-mode noise, ensuring robust operation in electrically noisy environments. In backplane systems, where multiple modules and cards operate in close proximity, this is a critical advantage.   Signal Integrity Over Distance LVDS maintains strong signal integrity over long traces, connectors, and through-plane vias. Its low EMI profile minimizes interference with adjacent channels, enabling high-density, multi-channel backplane architectures.   Compatibility and Ecosystem Support LVDS is supported by a wide range of FPGAs, ASICs, and SerDes transceivers. This wide ecosystem simplifies system design and integration, offering flexibility across generations of products.   Low Electromagnetic Interference (EMI) Because it uses tightly coupled differential pairs with small voltage swings, LVDS generates very low EMI. This not only aids in regulatory compliance but also reduces the likelihood of inter-channel interference in compact designs. LVDS combines speed, efficiency, and reliability, making it a strong choice for modern backplane applications.   Packet Data format The data is transmitted in the data link by packet. The Packet is consistent with Preamble, Command, ID, data, and parity bit to ensure a quick and reliable transmission. The details of the data packet can be defined in the following table: Definition Length Value Preamble 3 bytes 24'hAA _AA_AA Comma Symbol 1 byte 8'hBC/DC/FC/7C Frame type & Slave quantity 1 byte 2'hxx & 6'hxx Slave data length (bytes) 1 byte 8'hxx 2 bits Reserved & Slave lD 1 byte 2'h00 & 6'hxx Slave0 data 1~256 bytes 8'hxx…8'hxx Slave1 data 1~256 bytes 8'hxx…8'hxx …… …… 8'hxx…8'hxx SlaveN data 1~256 bytes 8'hxx…8'hxx CRC16 Checksum 2 bytes 8'hxx, 8'hxx Error Indication 1 byte 8'hxx   4 Module Architecture   When implemented in a Master/Slave type of data transmission application, the Master and Slave logic will be implemented differently. The following examples are utilizing the general IDES and OSER logic block in every IO of all GOWIN FPGAs to perform the downstream and upstream data transfer and utilize the FPGA fabric to implement the CRC16 and 8b10b encoder/decoder logics. The typical performance is 100MHz LVDS signaling. For the GW5A series FPGAs, GOWIN’s EasyCDR® technology can be utilized for downstream and upstream data transfer. Therefore, Gigabits per second data rate can be achieved. The Master Controller primarily consists of a control logic module, a CRC check module, an 8B/10B encoder/decoder module, a data serialization module, a data oversampling and recovery module, and a phase-locked loop (PLL). According to the data flow direction, these modules form the downlink and uplink transmission paths. The Slave Controller primarily consists of a control logic module, a CRC check module, an 8B/10B encoder/decoder module, a data serialization module, a data oversampling and recovery module, and a PLL. According to the data flow direction, these modules form the downstream (input from the upstream port and output to the downstream port) and upstream (input from the downstream port and output to the upstream port) transmission paths, respectively.     Typical Resource Utilization For Master controller LUT4 FF BSRAM Target Device 672 410 1 All GOWIN FPGAs   For Slave controller LUT4 FF BSRAM Target Device 1683 991 2 Device with 2K and above logic resource   Solution Highlights LVDS data is transmitted with an embedded clock. Clock Data Recovery uses hardened blocks such as IDES, OSER, or EasyCDR® blocks in every IO of the GOWIN FPGA Implemented 8b/10bencoding and decoding and CRC parity bits to improve the reliability of data communication The data rate can be up to Gigabits per second The current version of GOWIN IP can support 1 Master, up to 64 Slave modules The data packet size is up to 256 Bytes with the current version of IP The master module can support communication via Unicast Frames Supports the Slave synchronization function Master can identify the total Slave module number, and the last Slave module can self-wrap around Slave can self-diagnose when the data link is interrupted. Keeps the system online when performing such action, increasing system robustness   5 Typical Applications   (I) Simplifying Industrial Networking with GOWIN’s Gigabit LVDS solution   In the evolving landscape of industrial automation, system performance, wiring complexity, and cost are critical factors in network design, especially for fieldbus protocols like EtherCAT®. GOWIN Semiconductor addresses these demands with its Gigabit LVDS Datalink with Embedded Clock, a high-speed, low-latency communication solution designed to simplify network expansion and enhance performance.   A Smarter Way to Extend EtherCAT® Slave Networks Traditional methods of extending EtherCAT® slave node networks often rely on complex Ethernet-based cable and hardware, which can introduce latency, increase costs, and complicate installation in space-constrained or harsh industrial environments. GOWIN’s Gigabit LVDS Datalink provides a streamlined alternative.   By utilizing Low Voltage Differential Signaling (LVDS) with an embedded clock, this solution enables high-speed serial data transfer over simple point-to-point connections, eliminating the need for external clock routing and reducing pin count. This makes it ideal for expanding slave nodes in a compact, deterministic, and low-cost manner.     Shown above is a representative application of the LVDS bus system, which typically serves as a low-cost and efficient extension to Industrial Ethernet nodes, enabling simpler and more flexible physical-layer communication.   Key Advantages Simplicity in Wiring: The embedded clock feature removes the need for a separate clock signal line, reducing cable complexity and connector size. Ultra-Low Latency: The direct and deterministic nature of LVDS transmission ensures minimal delay, supporting real-time industrial control. Cost-Effective: With fewer components and simpler PCB and cable design, system costs are significantly reduced. High Throughput: Gigabit-level data rates support demanding industrial data exchange needs. Ideal for Industrial Applications Whether used in robotics, motion control, or factory automation systems, this solution enables manufacturers to extend EtherCAT® slave networks efficiently while maintaining strict performance and timing requirements.   (II) Multi-dimensional control in Humanoid Robotic Systems Humanoid robotic hands aim to replicate the dexterity and adaptability of human fingers, but this involves a series of complex challenges. Here's a brief look at the main hurdles engineers face:   Complex Mechanics Human fingers have multiple joints and degrees of freedom. Replicating this requires many actuators and precise coordination, making both design and control complicated. Miniaturization Fitting motors, sensors, and wiring into the small size of human-like fingers is technically demanding, often limiting design options. Tactile Feedback Accurate touch and force sensing is essential for manipulation but difficult to achieve at small scales with sufficient sensitivity and robustness. Control Algorithms Robotic fingers must handle nonlinear dynamics and tightly coupled joint motions. Advanced control strategies are needed to ensure stable, responsive movements. Dexterous Grasping Grasping varied objects reliably remains a tough problem. It demands smart integration of vision, touch, and motion planning in real time. Power Constraints High-performance actuators use significant energy, creating trade-offs between power, size, and battery life in humanoid designs. In Summary Humanoid robotic finger control requires solving intertwined problems in hardware, sensing, and control. A simplified, high efficiency, low power, low-cost network is required for such challenges. Here is our proposed network scheme that can meet these requirements.   In the above diagram, multiple motors need to be acting in Sync with the sensed data from the action point. The host is acting as a central command unit. Based on data feedback from the action fields, it sends out action commands to each motor. To carry out such tasks, a dual datalink network formed by multiple FPGAs, as mentioned in this article, are used. Each of the nodes is consistent with one motor, at least one sensor, and one FPGA connected to them. The FPGA is facilitating sensing, motor control, and data communication tasks. The ideal devices that can deal with all these tasks are probably GOWIN’s GW5AS-LV25 or a smaller one, GW1NS-LV4. The downstream datalink carries out the commands from the Host, and each node receives such a command, acting on it to control the motor to perform as designed tasks. The upstream datalink transfers the sensor’s data back to the host so that it can calculate what the next action needs to be sent out. In conclusion, such a solution provides low latency, high speed, low cost, low power, and simple wiring that can meet the challenges in this field. 6 Supported GOWIN Devices and IPs   This solution is available across the full range of: GW5A series with EasyCDR® running up to Gigabits per second GW1N series typically runs at 100MHz GW2A series typically runs at 100MHz GOWIN provides: Reference Designs and IP for rapid prototyping   7 Conclusion   GOWIN’s Gigabit LVDS Datalink with Embedded Clock solution offers a compelling alternative to traditional industrial networking methods. By addressing the key limitations of conventional systems, such as high costs, complex wiring, and integration challenges, this solution delivers substantial value to engineers and system designers working in industrial automation, robotics, energy systems, and intelligent transportation. Unlike conventional Ethernet-based solutions that often require specialized switches, bulky cabling, and intricate configuration, GOWIN’s approach simplifies implementation through embedded clocking, point-to-point LVDS signaling, and a scalable FPGA architecture. The result is a low-cost, low-latency, and high-speed communication platform that enables real-time data transfer with excellent noise immunity and minimal electromagnetic interference (EMI). With support for up to 64 slave nodes, packet-based transmission with CRC error checking, and gigabit-level throughput using EasyCDR® technology, this datalink architecture is well-suited for modern industrial environments that demand precision, reliability, and flexibility. Ultimately, GOWIN’s LVDS solution not only enhances system performance but also reduces time-to-market and total cost of ownership, making it an ideal fit for customers seeking efficient, robust, and future-ready connectivity in their next-generation industrial designs.   8 Reference   IPUG1219-1.0, 06/27/2025 LVDS Data Transmission System with Embedded Clock Design Guide-For Internal Use EasyCDR® White paper GW5AS-LV25UG256 data sheet Trademark Acknowledgments: EtherCAT® is a registered trademark and patented technology, licensed by Beckhoff Automation GmbH. EasyCDR® is a registered trademark of GOWIN Semiconductor Corp.   Support and Feedback GOWIN Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below. Website: www.gowinsemi.com E-mail：support@gowinsemi.com Revision History Date Version Description 2025/06/30 1.0E Initial draft   Copyright © 2025 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.   Gowin, LittleBee, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.   Disclaimer GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

Excited to announce our collaboration with @motsai research Inc. on their latest E-book: "MicroFPGA Advantages for System Integration." Explore how our LittleBee Device elevates #safety protocols, boasts 480 MBps #usb capabilities, integrates an ARM Microcontroller for seamless device setup, features rapid PLLs for precise clock generation, delivers short pulses, and facilitates high-speed ADC interfaces—all at a minimal cost to your BOM. These self-contained ICs are truly captivating.   Moreover, GOWIN FPGAs power high-speed, low-latency sensors, enabling them to capture intricate information streams effortlessly.   A heartfelt thank you to Motsai for spotlighting our LittleBee device in their comprehensive E-book on the advantages of MicroFPGAs.   To dive into this invaluable resource, download the Ebook for free here: 

White Paper   Table of Contents   Scope Introduction to MIPI GOWIN MIPI solutions overview  Hardcore MIPI PHY IPs GPIO-based MIPI PHY IPs GOWIN MIPI PHY and Protocol layer IPs and reference designs Conclusion Version History     1   Scope   This document is trying to give a comprehensive overview of GOWIN’s MIPI solutions capability to help users choose the best device for their design. Users need to work together with other GOWIN User Guides and Application notes in their detailed implementation.   2. Introduction to MIPI   The mobile industry processor interface (MIPI®) standard defines industry specifications for the design of mobile devices such as smartphones, tablets, laptops, and hybrid devices. It is developed and maintained by Alliance, which is a global business alliance that develops technical specifications for the mobile ecosystem, particularly smartphones including mobile-influenced industries. GOWIN Semiconductor Corporation is a member of the MIPI Alliance.   For years, MIPI has been pretty much synonymous with mobile phones. But as higher-resolution image sensors increasingly are deployed in AI, IoT, automotive, and medical devices, interest in MIPI is spreading well beyond its core market. While standardized signal protocols and characteristics are becoming essential, an explosion of low-cost, high-performance image sensors for a growing number of applications is propelling the MIPI interface into a variety of new markets.   The MIPI standard defines four unique physical (PHY) layer specifications: MIPI D-PHY®, C-PHY®, M-PHY®, and A-PHY®. You can find detailed information and Specs from the MIPI Alliance Website.   MIPI® service marks and logo marks are owned by MIPI Alliance, Inc. and any use of such marks by Gowin Semiconductor Corp is under license. Other service marks and trade names are those of their respective owners.   3. GOWIN MIPI Solutions Overview   GOWIN has developed its MIPI D-PHY solution with its 1st FPGA device. Since then, various configurations and speed IP cores have been offered along almost all our FPGAs. GOWIN is the 1st FPGA vendor to offer MIPI C-PHY IP core in Arora-V family FPGAs. GOWIN is planning to offer M-PHY and A-PHY cores for the same Arora-V family FPGAs shortly. Below is an overview of the GOWIN MIPI PHYs. The detailed performance will be discussed in the following sections.   The Spec number listed in the document is from the best information to date. They are subject to be updated with future version releases.     The numbers here are subject to be updated with more testing results in house or in field.   4. Hardcore MIPI PHY IPS   GOWIN has developed the 1sthard MIPI D-PHY Rx core in their GW1N-LV2 device in-house. This IP core follows MIPI D-PHY Spec V1.1 with a maximum receiving data rate of 1.5Gbps.   In the next generation Arora V FPGA family, GOWIN has developed both D-PHY V1.2 at 2.5Gbps and C-PHY V1.1 at 2.5Gsps(5.7Gbps) for various devices. The detail feature is shown in the table below:     Below is the loopback test setup for the 25K device in the MG121 package:     Below is the Eye Diagram from 25K at 3Gbps testing results:     For C-PHY, below is the simulation results for the 60K C-PHY core, and test results will be published with the document update expected in Q2, 24.     One more interesting piece of information is longer distance applications. MIPI standard is optimized for smartphones and other portable devices where small spaces with short distances are expected. With GOWIN’s Hard IP, the equalization feature can give the user a boost when a longer distance is needed. The following user cases can be served as reference:   For GW1N-LV2, 5-meter-long SATA/HDMI/DP type wire, data rate at 500Mbps. For GW5A family, 2-meter-long CAT6 wire, data rate at 1.25Gbps   There are applications with cameras and displays at separate locations. With this capability, a single-chip solution becomes possible.     5. GPIO Based Soft MIPI PHY IPs   Due to FPGA’s programmable IO, many interfaces can be emulated by them with the help of external passive resistor networks. The great advantage of using GPIO-based MIPI PHY solutions is the flexibility. As mentioned at the beginning of this white paper, the MIPI Standard has gone beyond the traditional smartphone space. This flexibility compound with the FPGA ‘s programmability suits well for the diversity in the new application fields. Here are a few examples: The Mult displays inside an EV car could require 6~8 MIPI Tx ports; The VR or drone system could require 12 cameras as inputs and aggregate the data to one output. Few of today’s SOCs can handle such requirements. Below is a user case in a 3D printing system that utilizes 3 LCD methods.     Though many FPGAs today can support MIPI D-PHY, GOWIN’s FPGAs are 1st ones that can support MIPI C-PHY, MIPI M-PHY, and MIPI A-PHY by the patented technology.   MIPI D-PHY   The below diagram shows one implementation of a passive resistor network to emulate MIPI signaling. It is very important to take the trace and signal integrity to achieve the best performance.     For Gowin devices, the following maximum data rates have been achieved from in-house testing and customer reports:   For GW1N family C6 speed grade devices, Max data rate 900Mbps~950Mbps For GW1N family C7 speed grade devices, Max data rate 1.1Gbps~1.2Gbps For GW2A family C8 Speed grade devices, Max data rate 1.1 Gbps~1.2Gbps  For GW5A family C0 speed grade devices, Max data rate 2.0Gbps (2.5Gbps observed in house loopback testing on raw data) The maximum data rate is more related to internal clock performance than the GPIO. GW5AT-138/75 device has a max data rate of 1.6Gbps due to the local clock in a big die having relative underperformance to other devices.        b. MIPI C-PHY   GOWIN is the 1st FPGA vendor to offer a GPIO-based MIPI C-PHY solution through our innovative GPIO system. These IPs are only available for Arora V family devices. The following diagram shows GOWIN's patented GPIO-based MIPI CPHY soft IP solution. The following diagram shows the system architecture.   GOWIN is the 1st FPGA vendor to offer a GPIO-based MIPI C-PHY solution through our innovative GPIO system. These IPs are only available for Arora V family devices. The following diagram shows GOWIN's patented GPIO-based MIPI CPHY soft IP solution. The following diagram shows the system architecture.   Below is a more detailed Rx system implementation utilizing GOWIN’s EasyCDR® IP.     A loopback test has been set up and measured on a 25K device. Below is the bench setup:     The test results show a loopback of 800Msps speed has been achieved. The following are eye diagrams at 400Msps and 700Msps.     Due to the limitation on the trace length control in the test PCB, we believe a higher speed can be achieved. There are more data will be collected in the near future.       c. MIPI M-PHY   Compared to a traditional analog Serdes-based M-PHY design, the GPIO-based M-PHY is much lower in power, cost, and is more flexible. These IPs are under development and will be available for Arora V family devices. We are targeting the following:   HS-G1: 1.25, 1.45 Gb/s HS-G2: 2.5, 2.9 Gb/s       d. MIPI A-PHY   Compared to a traditional analog Serdes-based M-PHY design, the GPIO-based M-PHY is much lower in power, and cost, and more flexible. These IPs are under development and will be available for Arora V family devices. We are targeting the following:   Gear Data rate G1 Uplink   6. GOWIN MIPI PHY and Protocol Layer IPs and Reference Designs    GOWIN offers many PHY IPs as well as Protocols layer soft core IPs such as MIPI CSI-2, and MIPI DSI through the GOWIN EDA tool core generator.     7. Conclusion    GOWIN's MIPI solutions aim to assist users in selecting the most suitable solution for their design needs. By delving into the evolution and diverse capabilities of MIPI standards, it highlights how these interfaces have transcended their origins in smartphones to encompass a wide array of applications, including AI, IoT, automotive, and medical devices.   GOWIN's commitment to advancing MIPI integration is evident through its pioneering development of MIPI D-PHY solutions and its expansion into C-PHY, M-PHY, and upcoming A-PHY implementations within the Arora V family. This comprehensive range of solutions caters to various performance requirements and application scenarios.   The paper elucidates two key approaches adopted by GOWIN: the development of both hard and GPIO-based soft MIPI PHY IPs. While hard IPs ensure standards compliance and optimized performance, soft IPs leverage FPGA programmability, offering unparalleled flexibility to suit diverse application needs.   Performance benchmarks across different FPGA families underscore scalability and adaptability, demonstrating GOWIN's commitment to meeting varying performance demands. Furthermore, GOWIN's provision of Protocol layer soft core IPs, such as MIPI CSI-2 and MIPI DSI through their EDA tool core generator, enhances the breadth of their offerings, enabling seamless integration and design experiences.   Ultimately, this white paper serves as a practical guide, empowering designers to navigate GOWIN's versatile MIPI offerings effectively. By facilitating the integration of MIPI interfaces into diverse applications, GOWIN aims to support and propel innovation across industries.   8. Version History     Version Date Comments 1.0 Jan. 8th, 2024 Initial Release 1.1 March 29th, 2024 -Removing GW5A-45 from MIPI solutions overview table - Added * to GPIO bases for CPHY Rx column                                      

White Paper   Table of Contents   Abstract Introduction Features of GW1NZ Devices Typical Market and Applications Real World Example Unique Advantages and Market Positioning  Conclusion     1   Abstract   Data aggregation communication in battery-powered, space-constrained environments poses unique challenges, particularly in systems where multiple devices need synchronization. GOWIN's GW1NZ FPGA devices present an innovative solution, offering ultra-low power consumption, compact form factors, and versatile capabilities for seamless data aggregation. This white paper explores the features, applications, and advantages of GW1NZ FPGA devices in addressing these challenges.   2   Introduction   Numerous applications are in sync with multiple sensors spread across two or more subsystems. Each subsystem is usually an individual board. These sensor’s data need to be collected and added to the base system or main SOC. At the same time, the base system or main SOC needs to send commands or set parameters to these subsystems. These usually utilize low-speed protocols such as I2C, UART, SPI, etc and work as sideband communication channels in the system. The traditional method is simply following the protocol and results in many wires being used between the base system and subsystems.   Data aggregation refers to the process of combining information from various sources, thereby minimizing the need for numerous physical network connections between two communicating systems. Aggregate data is high-level data that is acquired by combining individual-level data. Combining the low-speed data and sending the aggregate data through a high-speed channel, can effectively reduce the number of wires between the base system and subsystems. It also reduces redundant data and helps lower the system's power consumption. One good example is the OCP DC-SCM project in server applications.   In scenarios demanding data aggregation under battery operation within limited spaces, conventional solutions often struggle due to power constraints and space limitations. These applications encompass a range of devices, including wearables and portables such as AR/VR devices, Smart Glasses, Cell phones, and more. GOWIN's GW1NZ FPGA devices stand out as a pioneering solution, surmounting these challenges with their distinctive features and capabilities.   3   Features of GW1NZ Devices   Ultra-low Power Consumption: The standout feature of GW1NZ devices lies in their ultra-low power characteristics, enabling standby power as low as 28uw and operational power below 10mW. This attribute makes them ideal for battery-operated applications demanding efficiency.   Cost-Efficiency: With the potential for large volume purchases to dip below $0.5/unit, GW1NZ devices offer a cost-effective solution without compromising on performance or functionality.   Compact Form Factor: The diminutive size of GW1NZ devices, as small as 1.8mm x 1.8mm, caters to the needs of handheld, portable, and wearable devices, providing flexibility in design and integration.   Instant On Capability: Leveraging the LittleBee Flash-based FPGA technology, GW1NZ ensures instant activation, crucial for seamless data synchronization and real-time operations.   Flexible Upgrade Options: The inclusion of the GoConfig IP enables background programming, facilitating easy field upgrades, ensuring adaptability, and future-proofing.   GW1NZ Series Table   Device GW1NZ-1 GW1NZ-2 LUT4s 1,152 2,304 Registers 864 2,016 Shadow SRAM (bits) 4K 18K Block SRAM (bits) 72K 72K PLLs 1 1 User Flash (bits) 64K 96K Max. GPIOs 48 125 Core Voltage (LV) 1.2V - Core Voltage (ZV) 0.9V 0.9V/1.0V/1.1V    Package Options, Availible User I/O, (and LVDS Pairs):   Package Pitch (mm) Size (mm) GW1NZ-1 GW1NZ-2 Identifier CG25 0.35 1.8 x 1.8 20 -   CS100H 0.4 4 x 4 - 88(27) H CS16 0.4 1.8 x 1.8 11 -   FN24 0.4 3 x 3 18 -   FN32 0.4 4 x 4 25 -   FN32F 0.4 4 x 4 25 - F QN48 0.4 6 x 6 41 41(12)     4   Typical Market and Applications   The versatile nature of GW1NZ devices finds application in various domains:   Battery-operated Applications: Given their ultra-low power consumption, these FPGAs are well-suited for devices reliant on battery power, ensuring prolonged operation without compromising performance.   High-Volume Consumer Electronics: The cost-efficient nature of GW1NZ devices makes them an attractive choice for high-volume consumer electronics, balancing functionality with affordability.   Handheld, Portable, Wearable Devices: Their compact form factor positions these FPGAs as an ideal choice for devices requiring a small footprint, enabling seamless integration into handheld, portable, and wearable gadgets.   Systems Requiring Synchronized Devices: Applications that demand synchronization among multiple cameras or displays benefit from the capabilities of GW1NZ devices, ensuring smooth data aggregation across the system.     5   Real World Example   The following diagram describes a portable device system:     The performance and power consumption of such a system are shown below:       6   Unique Advantages and Market Positioning    GOWIN's GW1NZ devices hold a competitive edge in the market:   Optimized Design for Thin Control Wires: These FPGAs efficiently handle complex signal transmissions, particularly in scenarios requiring thin control wires across split screens, ensuring robust data aggregation without compromising size.   Leading the Charge in Low Power, High Performance: In an era where cell phone makers seek solutions for efficient data aggregation, GW1NZ devices outshine competitors with their low cost, compact size, low power consumption, and high performance, potentially surpassing ASIC and other FPGA offerings.   Versatility in Multiple Applications: GW1NZ devices demonstrate versatility beyond cell phones, with potential applications in other multi-screen devices, highlighting their wide-ranging market potential.   Zero-Power Device and Adaptive Power Modes: Notably, GOWIN's zero-power device and support for multiple voltages make these FPGAs suitable for rest mode operations while excelling in full-power, always-on functionalities like in Opal devices.   GOWIN's GW1NZ family of FPGAs presents an all-encompassing solution to the challenges of data aggregation in battery-operated, space-restricted environments. Their unparalleled combination of low power consumption, cost efficiency, compact form factor, and robust performance positions them as a leading choice in diverse applications requiring seamless data synchronization and aggregation.   7   Conclusion   The GW1NZ family of FPGAs stands as an optimal solution for challenging scenarios where data aggregation is imperative in battery-powered, wearable, and handheld systems. Moreover, the adaptability of these devices to operate at reduced power levels further enhances their suitability for diverse applications.   The GW1NZ series, with its support for 0.9V Vcc, surpasses other FPGAs above a 28nm process, offering unprecedented efficiency. Tailored packages like the CS100H and CS42 cater to varying system complexities, providing scalable solutions with reduced power, cost, and size.                

White Paper   Table of Contents   Introduction Understanding Single-Event Upsets Advantages of GOWIN FPGA Solutions Rapid Error Correction Efficiency and Integration GOWIN 22nm FPGA SER Test Report Conclusion   1. Introduction  Field-Programmable Gate Arrays (FPGAs) are integral to today's electronics, offering unmatched flexibility and configurability. However, their reliance on SRAM cells for configuration introduces vulnerabilities to SEUs. This paper explores SEUs in FPGAs, highlighting why they must be prevented and how rapid correction is crucial.   2. Understanding Single-Event Upsets    SRAM Cells: The Heart of FPGAs   SRAM cells are the control centers of FPGAs, storing the Bitstream that governs their operation. Any change in the SRAM cell state can lead to catastrophic functional failures, making SEUs a grave concern.   Shrinking Transistors and SEUs   While SRAM cells often start from older technology, their susceptibility to SEUs increases as transistor sizes shrink to save die area. This downsizing reduces their ability to retain data, making them vulnerable to various external factors, especially in aerospace applications.   Cosmic Rays and Earth's Surface   Ordinarily, cosmic rays dissipate harmlessly in Earth's atmosphere, posing little threat to surface dwellers. However, SRAM cells' shrinking transistor sizes have led to concerns about even reduced cosmic rays causing SEUs, potentially leading to FPGA malfunctions.   Particles of Interest   Two primary particles causing SEUs are neutrons (mimicking cosmic rays) and Alpha particles, typically emitted by solder balls in packages. While changing materials is an option, it's often more economical to handle SEUs effectively.   3. Advantages of GOWIN FPGA Solutions    Strengthening SRAM Cells   Preventing SEUs begins with strengthening SRAM cells. GOWIN's innovative approach involves designing custom SRAM cells and enhancing their resilience. This measure significantly improves SEU resistance, even in smaller die sizes like the 22nm Arora V.   The 22nm BSRAM is till using TSMC foundry cells, there is a notable difference in the SER report. We do have hard ECC circuits for users to correct BSRAM SEU errors when reading out BSRM content. Comparative Performance   Comparing GOWIN's 22nm FPGA with competitors like Company X's 28nm 6 and 7 serials reveals GOWIN's superior SEU resistance. Comprehensive test data highlights this performance edge.   Controlled Testing   To quantify SEU resilience, controlled testing with neutron and Alpha particle bombardment is essential. GOWIN's failure rate data shows robust protection against SEUs, surpassing competitors and prior FPGA generations. Below is the comparison to Gowin’s GW2A 55nm Configuration SRAM cell which comes from TSMC 55nm GP process. (Ref TN713, GOWIN 22nm FPGA SER Test Report)     4. Rapid Error Correction    The Importance of Error Correction   For mission-critical applications, error correction is paramount. GOWIN employs a Hamming code-based error correction system, capable of detecting and correcting data errors.   Comparative Error Correction   GOWIN's error correction algorithm excels compared to Company X. Company X can only correct single-bit errors or adjacent two-bit errors (in advanced mode) per frame, while GOWIN's GW5A can correct a greater variety of two-bit errors per frame or multi-bit errors spanning multiple positions in the frame. Additionally, GOWIN's GW5A devices can report unrecoverable multi-bit errors, thereby enhancing the system's reliability.   Efficient Frame Size   GOWIN's FPGA frames are designed for efficiency, with significantly fewer bits per frame compared to Company X's. Smaller frame sizes reduce the risk of multiple-bit errors.   Some more information about the Frame size: 138K: Frame length: 1,513 bits 25k: Frame length: 469 bits 60k: Frame length: 918 bits Compared to Company X serial 7 Frame is 3,232 bits.   Dedicated Parabit   GOWIN integrates dedicated Parabits within the SRAM frame, simplifying error correction, no fabric function is involved for detection and correction operation. Gowin provides a simple wrapper IP – “SEU Handler” to make users easily access the SEU report and correction function. This approach enhances reliability and efficiency.   Customizable Scanning Frequency   GOWIN's FPGA solutions offer customizable scanning frequencies, enabling faster error detection and correction, crucial for uninterrupted operation, particularly in critical server environments. In advanced mode, the scan frequency can be up to 200MHz.   5. Efficiency and Integration    GOWIN's FPGA solutions integrate SEU mitigation features into the hardware, simplifying deployment for customers. This approach ensures efficient, reliable operations.   6. GOWIN 22nm FPGA SER Test Report   Test Background   GOWIN’s FPGA devices are SRAM-based, which means the user logic is programmed and controlled by internal configuration SRAM cells. A Single event upset of an SRAM cell, introduced by Alpha particles or Neutron particles, is well understood by the industry and needs to be considered in system failure rate calculations for mission-critical, functional safety, and high-reliability applications.   SRAM Tested   The number of SRAM cells can be derived from the bitstream file. The bitstream file contains all the data needed to be programmed into the FPGA SRAM cell array. Therefore, from the array size, we should be able to obtain the SRAM cell number. Such an array includes 2 types of SRAM cells: one is the configuration SRAM; the other is the block SRAM that users utilize for memory storage in their designs which does not involve the logic control. Table 2 and Table 3 show the soft error rates caused by single event upsets (SEUs) affecting memory cells used as configuration SRAM and block SRAM.   Test Methods   Neutron cross-sections are determined from CSNS beam testing according to the JESD89/6 Accelerated High-energy Neutron Test Procedure, and the thermal neutron cross-section according to the JESD89/7 Accelerated Thermal Neutron Test Procedure. The neutron soft error rate (in FIT/Mb) is corrected for New York City. Alpha particle cross-section is determined by Americium-241 source as alpha radiation source according to JESD89/5 Accelerated Alpha Particles Test Procedure, and the alpha soft error rate (in FIT/Mb) is corrected based on alpha emissivity 0.001 counts/cm2/hr.   Soft Error Rates for Configuration SRAM   Table 2 below shows the soft error rates caused by single event upsets (SEUs) affecting memory cells used as configuration SRAM.     ECC for Configuration SRAM   Gowin 22nm FPGAs provide ECC function, an experimental group was set up for ECC function capability verification. Under the same FLUX experimental conditions, with the SRAM readback frequency of 15MHz and the readback and comparison period of 44610us, SEUs can be observed during the readback process, in which SBUs are observed while no MBU is found. All observed SBUs are corrected by ECC circuitry, and the whole bitstream is maintained to allow the device to work normally.   7. Conclusion    GOWIN's GW5AT and GW5A family of FPGAs excel in preventing and correcting SEUs, outperforming competitors like Company X. With enhanced SRAM cells, efficient error correction, and dedicated Parabits, GOWIN offers a more reliable and efficient solution for mission-critical applications. Our FPGA solutions empower customers to deploy robust systems, even in the most challenging environments, with confidence.  

EasyCDR® - Tailored Solutions to Meet Your Specific Needs   White Paper   Table of Contents Introduction to Serdes Gowin EasyCDR® based Serdes by GPIOs EasyCDR© Solution advantages Application Examples Industrial Field Bus Potential Applications 7:1 LVDS MIPI M-PHY LVDS Bus Applications Conclusion     1. Introduction to Serdes SerDes, is a combination of the words Serializer and Deserializer. It enables the transfer of large amounts of information over coaxial or twisted-pair cables. In today’s world, the demand for higher-speed data transfer is on the rise, and parallel data flows are unable to keep up. SerDes technology can be used with either 50ohm Coax or 100ohm Twisted pair interfaces. In some cases, it is possible to transmit power over coax (POC), which is ideal for powering cameras. The key technology to enable data transfer in a single cable (copper or fiber) without a clock is Clock Data Recovery (CDR). When transmitting data to the cable, the data has been clocked out from the source, however, the clock signal is not sent out. Instead, the data stream has clock information indicated by data transition, called embedded clock. The key task is relying on the receiver end to recover the clock information by CDR technology. The general approach is to build a dedicated analog-based CDR system together with the transmit function to accomplish the entire SerDes function.   2. Gowin EasyCDR® based Serdes by GPIOs Easy Clock Data Recovery (EasyCDR®) is a groundbreaking technology designed to simplify data reception processes while significantly reducing complexity, power consumption, and cost. In essence, GOWIN’s new GW5A family incorporates an advanced I/O structure that can receive serial data with embedded clock signals. Our new Easy Clock Data Recovery (EasyCDR®) IP can de-serialize serial input data to output 10-bit or 16-bit parallel data plus the clock. This solution is entirely resident in the GPIOs and FPGA fabric, with no dedicated Analog Serdes involved.   GOWIN offers EasyCDR® capabilities in its 5A series chips, with impressive performance capabilities, up to 2.5Gbps. EasyCDR® 's simplicity and efficiency make it a superior alternative to analog SerDes solutions, which tend to be more power-consuming, complex, and costly.   Below is a diagram showing EasyCDR® working as an Rx function in Serdes.     3. EasyCDR® Solution advantages GOWIN's EasyCDR® solution stands out as a modern and efficient replacement for traditional analog Serdes solutions while the application speed requirement is under 2.5Gbps. Here are some key reasons why GOWIN's EasyCDR® is superior:   a. Versatility The EasyCDR® solution is based on the general resources of the FPGA instead of dedicated analog Serdes block, which makes it flexible and versatile. It can be implemented on all Arora V devices regardless of the availability of high-speed transceivers. Users can easily implement SerDes protocols to adapt to many different situations. Making it a valuable addition to many modern electronic designs.   b. Cost and Power Effectiveness The analog SerDes block is costly and consumes a lot of power. This is the reason only a few channel transceivers are available for each FPGA or with no SerDes at all. On the other hand, GPIOs are plentiful with less power and low cost to implement. EasyCDR® utilizes GPIOs and Logic resources of FPGAs, therefore, making it cost and power-effective.   c. Filling in Technological Advancement Gaps In today’s world, on one hand, leading-edge technology such as AI, smartphones, etc. drive the rapid advance of wafer process technology. On the other hand, technologies defined decades ago are still wildly used. For example, USB2.0 was introduced in the year 2000, and millions of such devices are still shipping now. The GPIO speed can easily surpass its 480Mbps speed now. Making a new tape out of the latest technology to support such a low-speed protocol just does not make sense, however, it is a SerDes-based protocol that traditional FPGA GPIOs cannot support. The EasyCDR® technology filled in the missing gap.   d. Greater Data Handling Capacity It is important for us to extend the speed envelope to support more applications. EasyCDR®'s ability to handle up to 2.5 Gbps sets it apart from competitors. Many user cases can be satisfied with such speed already.   4. Application Examples a. Industrial Field Bus Potential Applications Industrial field bus applications are crucial in the industrial sector for digital communication between instruments, controllers, actuators, and field devices. GOWIN's EasyCDR® can find applications in field bus systems that handle data exchange between field control equipment and advanced control systems, including standards like PROFIBUS, PROFINET, SERCOS, Modbus, and EtherCAT.   EtherCAT, in particular, has evolved to support high data rates such as EtherCAT G (1 Gbit/s) and EtherCAT G10 (10 Gbit/s). EasyCDR® can play a vital role in handling such high-speed data conversion applications, providing a reliable and cost-effective solution.    b. 7:1 LVDS 7:1 LVDS is commonly used in the connection of LCD panel driving signals. While EasyCDR® can meet the data rate requirements, it requires data with transitions for synchronization. To address this, techniques like 8B10B encoding or scrambling may be necessary to ensure continuous transitions in the data. However, it's worth noting that the market for 7:1 LVDS interfaces is decreasing as interfaces with embedded clocks, like eDP and V-by-One, gain popularity.   c. MIPI M-PHY MIPI M-PHY uses PWM signals and EasyCDR®. Being edge-based, it can recover the clock effectively. It provides synchronization capabilities for MIPI M-PHY, ensuring reliable data reception even when the clock rate is three times that of the data rate.     d. LVDS Bus Applications In LVDS bus applications, EasyCDR® simplifies connections by allowing data transmission without an additional clock signal. GOWIN's 5A and 5AT devices offer enhanced reception rates, extending up to 2 Gbps. This capability is crucial for meeting the increasing demands of higher data transfer requirements in industrial settings.     5. Conclusion GOWIN's EasyCDR® represents a cutting-edge solution for data reception that outshines traditional analog Serdes options at available speed range. With technological advancements, higher data handling capacity, power/cost-effectiveness, and versatility, EasyCDR® offers a superior alternative for various applications, including industrial field buses, LVDS interfaces, and MIPI M-PHY. As industries continue to demand faster and more efficient data reception solutions, EasyCDR® stands ready to meet these challenges while simplifying the design and reducing costs for electronic systems.   Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.   Gowin, GOWIN, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI.   Disclaimer   GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

IoT has introduced a large variety of devices that have their own unique system attributes.  According to a 2018 Ericsson Mobility Report， 1B cellular IoT connections were made in 2018, which is expected to grow to 3.5B connections by 2023.  Most of these unique IoT hardware systems have brought a new generation of security threats.  These threats now provide attackers access to more than just data – they provide localized control and monitoring of devices directly in the public environment which, if compromised, can jeopardize the safety of an individual or even the global.   Product security has vulnerability at all stages of production and procurement.  At the component level, devices can be compromised in the factory during testing, handling or shipment.  At the board level, modifications and vulnerabilities can be found during end product development, testing or manufacturing.  After the connected product is manufactured, the device is susceptible to reverse engineering, hacking and cloning. All of these situations may lead to critical data being accessed, monitored or controlled.    In order to avoid these issues, one or more IC devices in the system need to establish a Root of Trust or RoT. These devices provide cryptographic capabilities to the system, which can be used for securely booting and authenticating firmware, generating or verifying keys, certificates and signatures, and encrypting or decrypting data.   The RoT device provides security capabilities to the rest of the system through a Chain of Trust.  As a result, it is the most critical device in the system from a security perspective since the entire system is vulnerable if it is compromised.  Evaluating the entire lifecycle of the RoT device from semiconductor manufacturing to product is important as a result.   Encryption functions use key pairs to identify and verify system functions.  Semiconductor manufacturers that produce IOT need to be able to establish a root key that matches the private key inside the IOT device, and the private key is inaccessible and never can leave the device.  If the private key is accessible in manufacturing, that device could be susceptible to cloning or hacking.  Additionally, if the private key is stored in the device’s flash or fuses, the key may be susceptible to retrieval in manufacturing or reverse in the design.   To solve these two problems, RoT devices should use a Physically Unclonable Function or SRAM PUF, which uses the intrinsic properties of an element in silicon as a truly random identifier.  This identifier can then be used to generate key pairs when the device powers up rather than storing it in a particular area which could potentially be reversed.  Additionally, to prevent cloning a certificate for the RoT, device should be issued on the manufacturing floor.  This certificate should have a signature based on the root key pair within the encrypted engine of the device.  With a signature from the manufacturer of the device as the certificate authority, the device can be validated as genuine to the system ensuring that the RoT device itself is not a clone.   Compliance to standards is also important to ensure that security elements in the RoT device are compatible with the rest of the system.  As a result, in addition to complying with the standards set by the National Institute of Standards and Technology, SP 800-90 compliance for random number generation and SP 800 193 for Platform Firmware Resiliency or PFR are important factors for both security and compatibility.   Security and RoT Device Options   Historically, there have been two options for security devices in a given system: MCU and FPGA.  Both of these systems have advantages and disadvantages.  MCU has the advantage of ease of use, and it is much easier to license libraries and APIs that are more easily transplanted from one device to another.  A good example of this would be something like FreeRTOS and MBED TLS, which has become widely used for embedded IoT systems to gain TCP/IP and TLS/SSL.  One disadvantage to the MCU is IO available, which can cause limitations to the number of interfaces needed to provide security features over the entire system.  Another disadvantage is the MCU’s ability to check its own boot memory during runtime.    FPGA has a large number of IOs, low latency and the ability to check system components in parallel. A large number of IOs allows you to control and monitor more components in the system, low latency allows you to check system components faster, and parallel computing allows you to faster check the overall system.  However, its main disadvantage is that it is not as easy to use as MCU.  For example, enabling TCP/IP and SSL stacks in the FPGA without a processor and significant memory would be extremely challenging and likely not a priority for the OEM.   Ultimately, the ideal device would integrate security features into devices with both an MCU and FPGA fabric at a low cost and lower power.  It would also have the right packaging needed for an array of applications from edge devices to the Server.  This would provide the advantages of both historical options and optimize the system based what’s required.  Fast power up and parallel checking can be achieved by taking advantage of the FPGA fabric, while the MCU’s ease of use and library integration can enable faster development time.   Gowin SecureFPGATM – Secure µSoC FPGA for RoT in Edge, IoT and Server Systems   The latest innovation in RoT device security is Gowin SecureFPGATM, which combines the advantages of the MCU and FPGA with the security functions needed for edge, IoT and Server applications.  SecureFPGA provides a security library based on SRAM PUF technology with Gowin genuine device authentication designed to eliminate attacks from the factory floor to the daily use of the end product.   The device has a wide range of packaging including BGA, QFN and TQFP to meet the needs of IoT and Server applications. There are different IoT packages. Server packaging is available such as QFN, BGA and TQFP depending on the application.     Full-Featured Security Library   Gowin SecureFPGATM intends to solve and eliminate issues with current security devices by providing a full-featured security library along with a secure component based on SRAM PUF technology and Elliptic Curve Cryptography or ECC. Additionally, Gowin has cooperated with Intrinsic ID to offer the BroadKey-Pro security library. Developers can use encryption tools to create a RoT for applications in Gowin SecureFPGA devices, or use proven and mature security solutions to provide a RoT for multi-device systems   Figure 1 GW1N-9C SecureFPGATM Device   Gowin SecureFPGATM Security Capabilities     Bitstream Lock - Removes the possibility of off-chip reading device bitstream Factory Provisioning - Activates code, UUID, CSR and Certificate Internal Dual Boot Flash - Online and remote upgradable with firmware signature checking SRAM PUF - Root devices keys generated at powerup; never stored in Flash UUID - Unique Device Identifier signed with the SRAM PUF root key pair Device Certificate - Validates device as a genuine Gowin device signed with SRAM PUF root key pair ECDH Encryption/decryption - AES128/192/256 Engine based on ECC Key Pair codes; SRAM PUF device unique or random. Asymmetric key pair generation - Based on SRAM PUF device, unique or random. ECDH Symmetric key generation - Based on SRAM PUF device, unique or random. ECDSA Signature - Generation and Verification Random Number Generator - Based on SRAM PUF and AES   Security Solution Maturity, Compliance, and Certificates   GOWINSEMI has cooperated with Intrinsic ID to offer the BroadKeyPro security library within Gowin SecureFPGA devices.  Intrinsic ID provides one of the most mature SRAM PUF technology solutions in the industry and has been adopted by many semiconductor device providers.     It has been recognized in the industry for several years and recently was named IoT Security Product of the Year in the 2019 IoT Breakthrough Awards. It has been shipped into over 125 Million IoT devices, and meets the requirements of FIPS 140-2 Appendix B and China’s OSCCA standards.  Lastly, it has been deployed in everything from banks to banks, setting a high standard for security in RoT capable devices. The certificates include EMVCo, Visa, and CC EAL6+.   Typical Applications Secure Boot and Secure Software Update Secure boot is the process of hashing and generating a signature using a key and then verifying it versus a signature created at an earlier time, then the device can check whether the firmware has been tampered  before executing it.    Figure 2 Secure Boot   For embedded applications, the secure boot starts by generating a signature over the firmware using the private key of a key pair. This signature is stored in the device for comparison at runtime. Once a signature is generated and stored, a small set of boot code can generate a signature using the public key and verify it versus the signature previously generated and stored in the device.   Figure 3 SecureFPGATM - Secure Boot Preparation   Figure 4 SecureFPGATM - Secure Boot Verification   It also can be applied for verifying firmware for multiple devices on a server.  Each firmware has a signature generated by the private key of the pair. Then at power up, Gowin SecureFPGA validates signatures of each firmware for each device.   Figure 5 Gowin SecureFPGATM for Secure Boot in Server Applications     In addition to device secure boot and server secure boot applications, it also can be used for secure firmware updating.  In this case, firmware is signed by the source and sent to a device over some medium such as the web or a cable.  The device can then use the public key to verify the firmware before switching to it or retain the use of its base image.   Figure 6 Secure Firmware Update   Data Encryption   There are many applications that have a need for encrypting data.  For example, a device can individually encrypt or decrypt data or firmware in its flash or ram so plaintext is never stored.  Another scenario is that a device can exchange encrypted or decrypted data with another device with exchanged keys so that the data will not be leaked during transmission.   Figure 7 Gowin SecureFPGATM Internal Device Encryption/Decryption Flow   Figure 8 Gowin SecureFPGATM Device to Device Encryption/Decryption Flow   Manufacturing    To ensure security over the entire manufacturing process, GOWINSEMI has special SecureFPGA equipment. SecureFPGAs are provided with an activation code during test time, which enables the device to always generate the same root key pair. The root private key that is generated with the SRAM PUF engine is never exposed to the user or outside the device.  It is only available to security functions in the device and called by the user through key codes.  During configuration, the root public key is exported from the device.  A Certificate Signing Request or CSR and UUID for the device are formed, which can be used with a third party CA.  Optionally, Gowin provides a Certificate Authority (CA) service to generate the certificate for each device in the factory.  Gowin CA service provides the ability to confirm a device is genuine by validating the devices unique certificate or repudiating; if not genuine, please contact Gowin technical support. These features provide assurance that the device has a unique identity; it is genuine and does not contain content in flash that may be vulnerable to be attacked from factory floor to end of product life.   Conclusion   Gowin SecureFPGA products provide a Root of Trust based on SRAM PUF technology. These devices are virtually impossible to duplicate, clone or predict. This makes them very suitable for applications such as secure key generation and storage, device authentication, flexible key provisioning and chip asset management.  Each device is provided with a unique key pair that is never exposed outside the device or during device development or manufacturing. The Intrinsic ID BroadKey-Pro security library is provided with Gowin SecureFPGA devices, allowing easy integration of common security features into user applications. Gowin SecureFPGA is used widely for a variety of applications such as consumer,  industrial IoT, edge, and server management.    Related Material     Columbus, Louis. “2018 Roundup Of Internet Of Things Forecasts And Market Estimates.” Forbes, Forbes Magazine, 18 Dec. 2018, www.forbes.com/sites/louiscolumbus/2018/12/13/2018-roundup-of-internetof-things-forecasts-and-market-estimates/#4b33a2747d83.   2. Lazich, Milan. “Intrinsic ID's BroadKey Named 'IoT Security Product of the Year' in 20.” PRWeb, 3 Jan. 2019, www.prweb.com/releases/intrinsic_ids_BroadKey_named_iot_security_product_of_the_year_in_2019_iot_breakthrough_awards/prweb16012275.htm.    Technical Support   Gowin Semiconductor provides customers with comprehensive technical support assistance. If you have any questions, comments, or suggestions, please feel free to contact us.   Website: www.gowinsemi.com E-mail: support@gowinsemi.com   Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.   GOWIN, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI..   Disclaimer   GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. All information in this document should be treated as preliminary. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata.

The amount of responsibility given to and expected from edge devices is growing rapidly in all types of automotive, IoT, industrial, and consumer applications. Edge inference is becoming a common capability in these devices to provide localized decision making, reduced latency and cost reduction of connected nodes.   These solutions often struggle to meet the next set of customer demands on cost, power, size as well as the flexibility to adapt and integrate over time. Additionally, the heavy computational needs of neural networks often push beyond the performance of standard microcontrollers. They also struggle from meeting time to market pressure while being expected to incorporate the latest technology advancements.   Low density FPGAs can be used to address common customer constraints on cost, power and size by providing flexible and scalable solutions dependent on the network size.    GOWIN FPGA’s specifically address this by providing scalable device densities from 1k to 55K LUTs in variety of wafer level, QFN, and BGA package options as small as 3.24mm2 on both low power and high performance process technologies.     To improve performance and time to market of developing edge solutions for artificial intelligence GOWIN has created a new acceleration IP and solution suite called “GoAI” targeting their FPGA devices. The GoAI solution suite integrates GOWIN’s AI acceleration IP into existing machine learning frameworks to improve performance by over 78x compared to using a Cortex-M class microcontroller alone.     Usage of Edge AI in the System     Artificial intelligence at the edge is typically used for one of two purposes in a system. The first is to perform inference with devices that have no connectivity to the internet. These systems use machine learning to detect some information about an input and utilize it to control outputs of the system that are connected to it.       The second purpose is used to perform some pre-detection before sending data to the cloud for further processing. This can be done for various reasons such as saving power by shutting off the wireless transceiver or cost by only sending data to cloud AI services when some pre-detection has occurred.     Deploying AI at the Edge   Artificial intelligence today uses the machine learning techniques centered around convolutional neural networks. These networks are essentially sets of many filters or “neurons” with coefficients or weights that are trained to identify certain key attributes of an input. These weights are calculated through a process called “training” where a set of inputs are provided, the output is known and the weights are updated to identify it.   Training a convolutional neural network often consumes a significant amount of computational power. However, since it is only used to generate the weights to infer certain attributes about the input it generally does not need to run in real time. Once a network is trained the weights can be loaded into a network to detect attributes related to the input.  This inference often requires significantly less computing power than training.   While the computational power is significantly less for inferencing it often still exceeds the performance of microcontrollers. This is because microcontrollers process each computational instruction per processor clock cycle often in the sub-200Mhz range which is not enough performance to make detections of even small machine learning networks in real-time. Additionally, many use cases related to AI require specialized interfaces and buffering of data. For example, camera data often needs to be stored in RAM as a frame since filtering is performed over multiple pixels within the image at the same time.   Edge focused FPGAs address these problems easily. Parallel and pipelined computations of the network allow for real-time performance while operating the system more efficiently at 10’s of Mhz. Flexible interfacing allows the FPGA to connect to cameras, microphones, biometric sensors and other inputs easily. Configurable memories allow for buffering and retention of intermediate or layer data.   While FPGA’s provide a great avenue to make edge AI possible, a strong software stack is needed to make development and deployment easy. Modeling software for neural networks is available by several providers; Tensorflow, Caffe and Keras are common names.  These networks are often natively developed using floating point computations for training and testing by the software, which causes issues when attempting to deploy a cost and performance worthy solution at the edge.   As a result, common deployment tools such as Tensorflow Lite for microcontrollers and Arm CMSIS-NN use an optimization process to truncate and quantize trained weight data from floating point to 8-bit fixed point, making the resources more practical for edge focused hardware. However, the performance is often still significant and as result an accelerator design specifically to pipeline the convolutions and accumulations of layer data is common.  These accelerators can be designed in ASIC or FPGA to improve things further to real-time performance.     A System Example     To run through an entire development flow from model training to hardware design the GoAI platform was used to perform image detection on the CIFAR10 dataset. The performance of the GoAI accelerator was compared to an Arm Cortex-M microcontroller running the same network in CMISIS-NN. The CIFAR10 dataset is a common dataset of 10 classification objects used to measure various performance attributes of a machine learning system.   First, a network was trained for the system in Caffe. In this case, the network tested used three convolution layers with varying numbers of filters. After the network was trained, coefficients for weights and bias were obtained and the trained network was tested in Caffe over various inputs to ensure it behaved as expected.   After that the weight and bias coefficients were truncated and quantized using script utilities and the network was compiled to use CMISIS-NN function calls on an ARM Cortex-M1 and M3 processor. The optimized network was then deployed on the ARM Cortex-M1 processor with a camera interface and frame buffer connected to the AHB bus. The neural network took approximately 10 seconds to process one image from the camera.   Next, the GoAI accelerator was connected to the AHB bus and used to process the network. The Cortex-M1 was still used to pass image data initially to the accelerator, load weights and bias and configure the accelerator settings. The neural network took approximately 0.5 seconds to process using the GoAI accelerator with delays primarily associated with the results sent over UART.     Further analysis was performed on the Arm Cortex-M3 processor and the accelerator.  The difference between using the Arm Cortex-M3 processor by standalone versus with the GoAI accelerator showed an ~78x performance improvement.   GoAI 2.0     GoAI 2.0 focuses on: Integration of the FPGA accelerator with TensorFlow and TensorFlow Lite Targeting the GOWIN GW1NSR-4C uSoC FPGA with Cortex-M3 hard processor in 6x6mm QFN package Software compiling and deployment SDK’s Flexible architecture for supporting a variety of models with large number of layers and large layer depth   The GoAI 2.0 platform uses standard TensorFlow development environments to allow training and testing of any model. The final trained model then uses TFLiteConverter or TocoConverter to parse and quantize the model into a *.tflite flatbuffers file. The flatbuffers file is then parsed using the GoAI 2.0 SDK to extract model coefficients, layer parameters and model functions.   After extracting all the necessary information from the flatbuffers file, the GoAI 2.0 SDK loads coefficients to external SPI flash memory, C code to the embedded flash of the Cortex-M3 and bitstream to the FPGA in the GW1NSR-4C device or other supported GOWIN FPGA.     The architecture of the GoAI 2.0 platform allows for as deep of layers as there is PSRAM embedded in the GW1NSR-4C and as many convolution and pooling layers as there is memory to hold layer parameters. The GW1NSR4 has 8MB of PSRAM, which is split into a 4MB input layer buffer and 4MB output buffer layer. This means that a layer input and output can be up to 4MBs in size. The ITCM embedded flash within the Cortex-M3 is 32KB, which only needs to hold the control loop and the filter parameters for each layer. The external SPI flash holds the weight and bias coefficients for each layer and can be adjusted depending on the model size required.     Testing of the GoAI 2.0 platform was performed using Mobilenet v1.025 and the COCO dataset. Mobilenet is a fairly large convolutional neural network with 28 layers. 162ms inference latency was achieved using GoAI 2.0 with this model.     Conclusion   Various challenges arise while attempting to efficiently perform AI at the edge within a reasonable cost, power, size and time to market budget. Artificial intelligence at the edge is becoming increasingly important for both unconnected and connected devices. Edge AI solutions require an accelerator and complete software development flow to perform real time processing and integration into common machine learning model development software. GOWIN’s GoAI accelerator and software solution stack provides an ideal solution to address both performance and market environment constraints. 

Device connectivity at the edge has become a necessity. About 4 Billion devices in 2018 shipped with Bluetooth technology according to Bluetooth SIG, which is expected to continually grow at a compound annual growth rate of 12% over the next 10 years. This high continual growth is backed with new capabilities and use cases for the standard such as point of interest broadcasting, indoor navigation, transfer and recording of sensor and communication data, control, monitor and automation systems.   Most Bluetooth devices come in two forms. The first focuses on providing only a radio with an interface that can be controlled by a separate microprocessor. The second has a Bluetooth radio as well as a microcontroller in the same device that can be used for the Bluetooth stack as well as a limited amount user applications. These integrated solutions are often limited on what capabilities the microcontroller can offer as a result of specialized market needs.   Standalone Bluetooth Device   Intergrated Bluetooth Device   Additionally, both devices often lack flexible IO. For example, camera and display interfaces are rare at the microcontroller level and audio interfaces such as I2S may be extremely limited or non-existent. Sensor interfaces may be limited by the small number of IO available as well.     Performance can also be limited. Many times the processor in Bluetooth devices is limited to the lowest performance to save power. In cases, where the processor has more performance the power can be high for always-on use cases which require continual monitoring and control of the system such as data streaming or driving motors.   These deficiencies could be remedied by the benefits seen in edge focused FPGAs.  However, there is no FPGA to date with an integrated Bluetooth radio so a two-chip solution must be used. This has board area, cost and integration issues that the developer must be concerned about when developing a new product.   As a result, GOWIN Semiconductor has created the first FPGA with an integrated Bluetooth 5.0 Low Energy radio called the GW1NRF. This integration enables the flexible and high IO count, always-on low power, acceleration and pipelining capabilities of an FPGA with the wireless data transmission capabilities of a Bluetooth radio in a single chip.   GW1NRF High Level Block Diagram   Additionally, integration of several other key features has been developed within the GW1NRF device. The device features a 32-bit power optimized ARC processor, which can be used for both the Bluetooth stack as well as user applications. It also features a power management unit capable of various power modes as well as power gating, reducing the total power consumption of the device down to 5nA. Additionally, the device features a step up/step down regulator to better enable the entire device to operate off a 1.5V or 3.0V battery. Security features are also provided such as a random number generator, AES-128 and a key generator.    GW1NRF-4 Device Block Diagram   Use Cases   The GW1NRF is a completely new device which promotes the ability for end product manufactures to innovate in ways that were never before possible. As a result, some possible use cases are discussed to promote the unique capabilities the device has in order to stimulate new product ideas.   Camera to Bluetooth   Camera interfaces are often not available on most microcontrollers and Bluetooth devices. Flexible IO of FPGAs allows for many types of image sensors to be connected with interfaces such as parallel/single ended CMOS or a serialized MIPI CSI-2.     Audio hub to Bluetooth   Many microcontrollers and Bluetooth devices either do not have enough digital microphone interfaces such as I2S or PDM for microphone array applications. With the flexible FPGA IO interfacing many microphones along with data communication via Bluetooth becomes possible in a single chip.      Bluetooth to Motor Control    Motor control over Bluetooth can provide control of robotic and industrial equipment from battery powered devices such as a smartphone. Having FPGA resources and flexible FPGA IO promotes control of multiple motors over Bluetooth in a singular device.     Bluetooth to LED Control    Controlling multiple LED’s with FPGAs is common due to high current drive IO and IO count. Adding Bluetooth within the same device provides remote control of LED arrays along with adjustments for intensity, color and generation of sequencing patterns.     Conclusion   The need for connectivity at the edge with Bluetooth Low Energy is increasing.  Programmable heterogeneous computing needs are also increasing for machine learning, computer vision and embedded graphics use case. Integration of programmable capabilities along with SoC features is also increasing in need to meet new power, size and cost requirements. As a result, the Gowin GW1NRF4 provides new capabilities with embedded Bluetooth Low Energy to enable the next generation of embedded computing devices.