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GOWIN RAM BASED SHIFT REGISTER

Gowin RAM Based Shift Register IP provides an efficient multi-bit width shift

register that can be used as a FIFO-like data buffer or delay line

function to create fixed-length and variable-length shift registers, as shown

in Table 2-1.

 

Features

  • Support GW1N, GW1NR, GW2A, GW2AR series chips.
  •  Can create fixed-length, lossy variable or lossless variable shift
    registers.
  • The speed of the variable length shift register can be optimized or the
    resource can be optimal.
  • Design support is based on LUT implementation, BSRAM implementation and SSRAM implementation.
Documents Download
RN512-1.0E Gowin RAM Based Shift Register Release Note Download
Reference Design Gowin RAM Based Shift Register RefDesign Download
Reference Design Gowin RAM Based Shift Register RefDesign Download
RD512-1.0E Gowin RAM Based Shift Register Reference Design Download
IPUG512-1.0E Gowin RAM Based Shift Register User Guide Download