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GOWIN PSRAM MEMORY INTERFACE

Gowin PSRAM Memory Interface IP is a common used PSRAM interface IP, in compliance with JESD79-F. The IP includes the PSRAM MC (Memory Controller) and the corresponding PHY (Physical Interface) design. Gowin PSRAM Memory Interace IP provides users a generic command interface to connect with the PSRAM chip for access and data storage.

 

Features

 

  •  Supports FPGA devices of GW1N-4, GW1NR-4, GW1NSR-2, and

 GW1NSR-2C;

  •  Interfaces with the standard PSRAM devices;
  •  Support memory data path width of 8 bits, 16 bits, 24 bits, 32 bits, 40

 bits, 48 bits, 56 bits, and 64 bits;

  •  Supports x8 and x16 data widths memory chips;
  •  Programs 16, 32, 64 or 128 burst lengths;
  •  The clock rate is 1:2
  •  The initial delay is six clock cycles;
  •  Supports the fixed delay mode;
  •  Supports the power off options;
  •  Configurable drive strength;
  •  Configurable self-refresh area;
  •  Configurable refresh rate.
Documents Download
Reference Design Gowin PSRAM Memory Interface RefDesign Download
IPUG525-1.1E Gowin PSRAM Memory Interface IP User Guide Download
RN525-1.0E Gowin PSRAM Memory Interface Release Note Download