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The Gowin DDR3 Memory Interface IP is an IP that is generally used for DDR3, which conforms to the JESD79-2F standard protocol. The IP includes the DDR3 memory controller (MC) and the corresponding physical interface (PHY) design. The Gowin DDR3 Memory Interface IP provides you with a generic command interface through which you can connect with the memory chip to access and save data.





  •  Supports the FPGA devices of GW2A-18,GW2AR-18 and GW2A-55;
  •  Connects to the industrial standard DDR3 SDRAM devices and
     modules that are compatible with the JESD79-3F specification;
  •  Supports memory data path width of 8 bit, 16 bit, 24 bit, 32 bit, 40 bit,
     48 bit, 56 bit, 64 bit and 72 bit.
  •  Supports the single row RDIMM UDIMM and SODIMM memory
  •  Supports x4, x8, and x16 data widths memory chips;
  •  Programs 4, 8, or OTF burst lengths;
  •  Supports clock ratio 1:2 and 1:4;
  •  Supports ECC;
  •  Configurable CL;
  •  Configurable AL;
  •  Configurable CWL;
  •  Configurable tFAW;
  •  Configurable tRAS;
  •  Configurable tRCD;
  •  Configurable tRFC;
  •  Configurable tRRD;
  •  Configurable tRTP;
  •  Configurable tWTR;
  •  Supports controlling the terminal ODT on the dynamic chip;
  •  Supports automatic refreshing and user startup refreshing,
     automatically refreshing the interval configurable.
Documents Download
Reference Design Gowin DDR3 Memory Interface RefDesign Download
RN281-1.0E Gowin DDR3 Reference Design Release Note Download
IPUG281-1.0E Gowin DDR3 Memory Interface IP User Guide Download