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The Gowin DDR2 Memory Interface IP is an IP that is generally used for DDR2, which conforms to the JESD79-2F standard protocol. The IP includes the DDR2 memory controller (MC) and the corresponding physical interface (PHY) design. The Gowin DDR2 Memory Interface IP provides you with a generic command interface through which you can connect with the memory chip to access and save data.




  •  Supports GW2A-18, GW2AR -18 and GW2A-55 FPGA devices.
  • Connects to the industrial standard DDR2 SDRAM devices and modules that are compatible with the JESD79-2F specification.
  • The clock ratio of DDR2 MC and PHY is 1:2.
  • Supports memory data path width of 8 bit, 16 bit, 24 bit, 32 bit, 40 bit, 48 bit, 56 bit, 64 bit, and 72 bit.
  • Supports the single row RDIMM UDIMM and SODIMM memory module.
  • Supports x4, x8, and x16 data width memory chips.
  • Programs 4 or 8 burst lengths.
  • Supports ECC.
  • Configurable CL.
  • Configurable AL.
  • Configurable tFAW.
  • Configurable tRAS.
  • Configurable tRCD.
  • Configurable tRFC.
  • Configurable tRRD.
  • Configurable tRTP.
  • Configurable tWTR.
  • Supports controlling the terminal ODT on the dynamic chip.
  • Supports automatic refreshing and user startup refreshing, automatically refreshing the interval configurable.
Documents Download
Reference Design Gowin DDR2 Memory Interface RefDesign Download
RN506-1.1E Gowin DDR2 Memory Interface IP Release Note Download
IPUG506-1.2E Gowin DDR2 Memory Interace IP User Guide Download