Listen to Your Voices and Let Us Know Your Needs

Gowin DDR Memory Interface IP is a common used DDR interface IP,
in compliance with JESD79-F. The IP includes the DDR Memory Controller (MC) and the corresponding Physical Interface (PHY) design. Gowin DDR Memory Interace IP provides the user a generic command interface to connect with the memory chip to access and save.



  • Support FPGA devices of GW2A-18,GW2AR-18 and GW2A-55; 
  • Support connecting to the industrial standard DDR SDRAM devices and modules compatible with the JESD79-2F specification;
  • Support selecting the clock ratio of DDR MC to PHY 1:1/1:2; 
  • Support memory data path width of 8 bit, 16 bit, 24 bit, 32 bit, 40 bit, 48 bit, 56 bit, 64 bit and 72 bit.
  • Support the single row RDIMM UDIMM and SODIMM memory module 
  • Support x4, x8, and x16 data widths memory chips; 
  • 1:1 programmable burst length 2/4/8, 1:2 programmable burst length 4/8;
  • Support ECC; 
  • Configurable CL; 
  • Configurable AL; 
  • Configurable tFAW; 
  • Configurable tRAS; 
  • Configurable tRCD; 
  • Configurable tRFC; 
  • Configurable tRRD; 
  • Configurable tRTP; 
  • Configurable tWTR; 
  • Support automatically refreshing and user startup refreshing, automatically refreshing the interval configurable


Working Frequency

Gowin DDR Memory Interace IP 1:1 mode can support 200Mbps, 266Mbps
and 333Mbps DDR SDRAM data rates; 1:2 mode can support 200Mbps, 266Mbps, 333Mbps, 400Mbps DDR SDRAM data rates

Documents Download
Reference Design Gowin DDR Memory Interface RefDesign Download
RN507-1.0E Gowin DDR Memory Interface IP Release Note Download
IPUG507-1.2E Gowin DDR Memory Interface IP User Guide Download