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STARTER KITS AND DEVELOPMENT BOARDS

To accelerate your innovation, start with our easy-to-use development kits and move swiftly from design concept to production.

GW1NSR2_工作區域 1
DK-START-GW1NSR2
Device Family
GW1NSR
Device
GW1NSR2
Price
--
Supplier
Gowin
GW2AR18_工作區域 1
DK-START-GW2AR18

 

 

Device Family
GW2AR
Device
GW2AR18
Price
--
Supplier
Gowin
Gowin GW1NS-2C MCU

The GW1NS-2C is an on-chip system consisting of an embedded microcontroller unit (MCU), field programmable gate array (FPGA) and the other standard peripherals. The embedded microprocessor system consists of a 32-bit microcontroller unit (ARM Cortex-M3 core) with low power and low cost, a bus system (including the AHB bus, the AHB2APB bridge and the APB1/APB2 bus), standard peripherals such as USB2.0 PHY, ADC, etc.,  and two AHB expansion bus (INTEXP0 and TARGEXP0, which offers a 126-bit AHB bus and connects to the user-implemented FPGA high-speed peripheral soft cores).

 

Features:

The MCU includes a Cortex-M3 core, a bus matrix, a Nested Vector Interrupt Controller (NVIC), and a debug access port (DAP). The NVIC provides two interrupt signals (USER_INT0 and USER_INT1) to connect to the FPGA, which is used for the interrupt control of the FPGA soft core peripheral. The DAP includes a JTAG debug access port and a Trace Port Interface Unit 0 (TPIU), both of which are connected to the FPGA.

The Cortex-M3 core accesses the MCU bus system (AHB bus, AHB2APB bridge and APB1, APB2) using the bus matrix. The AHB bus is connected to the FPGA and is used to access the 128-byte read-only Flash and the 8-byte read-write  SRAM via the memory controller. After the system is powered up, the Corttex-M3 loads the instructions and data from the Flash, transfers it to the SRAM, and then starts the program.

 

The embedded microprocessor system includes the following hard cores of standard peripherals:

 

  • A general-purpose I/O (GPIO) port connected to the FPGA via the AHB bus;
  • Two universal asynchronous transceivers (UART) connected to the FPGA via the APB1 bus;
  • Two TIMERs inside the microprocessor, which are mounted on the APB1 bus and accessed through the registers;
  • A WatchDog inside the microprocessor, which is mounted on the APB1 bus and accessed through registers;
  • The Interrupt Monitor connected to the FPGA using the APB2 bus, that feeds back the interrupt status of the current operation of the GPIO, UART and TIMER in the microprocessor system to the FPGA.
Device Family
GW1N
Device
GW1NS-2C
Price
--
Supplier
Gowin
DK-START-GW1NZ1 V1.1  board
DK-START-GW1NZ
Device Family
GW1NZ
Device
--
Price
--
Supplier
Gowin
START-GW1NS2
DK-START-GW1NS2
Device Family
GW1NS
Device
GW1NS-2C
Price
--
Supplier
Gowin
DK-START-GW1N4
DK-START-GW1N4
Device Family
GW1N
Device
GW1N-4
Price
--
Supplier
GOWIN
imageedit_4_6899932283
EVAL-pSRAM-GW1NR4
Device Family
GW1NR
Device
GW1NR-4.
Price
--
Supplier
Gowin
20180921_153135_HDR[1652]
DK-START-GW1N9

 

 

Device Family
GW1N
Device
GW1N-9
Price
--
Supplier
Gowin
DK-START-GW2A18 a[1649]
DK-START-GW2A18
Device Family
GW2A
Device
GW2A-18
Price
--
Supplier
Gowin
螢幕快照 2018-08-28 下午4.22.30
Gowin FPGA Download Cable
Device Family
GW1N/NR, GW2A/AR
Device
--
Price
--
Supplier
Gowin
擷取-01
Offline Programmer

 

 

 

Device Family
--
Device
--
Price
--
Supplier
Gowin