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LITTLEBEE ®

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GW1NZ Ultra Low Power FPGA

 

The GW1NZ series of FPGA products offer ultra-low power consumption, instant on, extreme low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer (especially mobile and wearable), etc.

 

Features

 Ultra low power consumption

  • 55nm embedded flash technology
  • - LV: Supports 1.2V core voltage
  • - ZV: Supports 0.9V core voltage (below 10uW standby power consumption with Power Management)
  • - Power Management Module
  • - Clock dynamically turns on and off

 

  • Power Management Module
  • - SPMI: System power management interface hard core

 

 User Flash

  • 64K bits
  • - Data Width: 32
  • - 10,000 write cycles
  • - Greater than ten years' data retention at +85 ℃
  • - Supports page erasure: 2048 bytes per page
  • - Duration: Max. 25ns
  • - Electric current

a). Read Operation: 2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX);

b). Write operation/erase operation: 12/12 mA (MAX)

  • - Quick page erasure/Write operation
  • - Clock frequency: 40MHz
  • - Write operation time: ≤16μs
  • - Page erasure time: ≤120 ms

 

 Multiple I/O Standards

  • - LVCMOS33/25/18/15/12;LVTTL33, PCI,
  • - LVDS25E,BLVDSE,MLVDSE,LVPECLE,RSDSE
  • - Input hysteresis option
  • - Supports 4mA,8mA,16mA,24mA,etc. drive options
  • - Slew Rate option
  • - Output drive strength option
  • - Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option - Hot Socket
  • - I3C hard core, supports SDR mode

 

 Abundant Slices

  • - Four input LUT (LUT4)
  • - Double-edge flip-flops
  • - Supports shifter register
  • - Supports shadow SRAM

 

 Block SRAM with multiple modes

  • - Supports Dual Port, Single Port, and Semi Dual Port
  • - Supports bytes write enable

 

 Flexible PLLs

  • - Frequency adjustment (multiply and division) and phase adjustment
  • - Supports global clock

 

 Built-in Flash programming

  • - Instant-on
  • - Supports security bit operation
  • - Supports AUTO BOOT and DUAL BOOT

 

 Configuration

  • - JTAG configuration
  • - Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

 

 

 


 

  • Low Power Non-volatile FPGA
 
  • Best in class of Performance Cost Ratio
  • Small footprint
  • MIPI standard supported
  • Embedded pSRAM (GW1NR/1NSR only)

 

Based on 55nm LP technology, LittleBee® family offers instant-on, non-volatile, low power, intensive I/O and small footprint FPGA (smallest as 2.4x2.3mm). The family is ideal for high-performance bridging application and the first FPGA supports MIPI I3C and MIPI D-PHY standard in the industry. The LittleBee® family is also the first non-volatile FPGA with an embedded pSRAM in the industry, which further reduces the board space

  • User Flash (GW1N-1)

- 100,000 write cycles

- Greater than10 years Data Retention at +85°C

- Selectable 8/16/32 bits data-in and data-out

- Page size: 256 Bytes

- 3μA standby current

- Page Write Time: 8.2ms

 

  • User Flash (GW1N-2/4/6/9)

- Up to 1,792Kbits

- 10,000 write cycles

 

  • Lower Power Consumption

- 55nm embedded flash technology

- LV: supports 1.2V core voltage

- UV: built-in linear regulator, supports1.8V, 2.5V, and 3.3V core voltage input

- Clock dynamically turning on/ turning off

 

  • Multiple I/O Standards

- LVCMOS33/25/18/15/12; LVTTL33, SSTL33/25/18 I, SSTL33/25/18 II, SSTL15; HSTL18 I, HSTL18 II, HSTL15 I; PCI, LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, RSDSE

- Input hysteresis option

- Supports 4mA,8mA,16mA,24mA,etc. drive options

- Slew Rate option

- Output drive strength option

- Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option

- Hot Socket

 

  • High Performance DSP

- High performance digital signal processing ability

- Supports 9 x 9,18 x 18,36 x 36bit multiplier and 54bit accumulator;

- Multipliers cascading

- Registers pipeline and bypass

- Adaptive filtering through signal feedback

- Supports barrel shifter

 

  • Abundant Slices

- 4 input LUT (LUT4)

- Double-edge flip-flops

- Supports shift register and distributed register

 

  • Block SRAM with Multiple Modes

- Supports Dual Port, Single Port, and Semi Dual Port

- Supports bytes write enable

 

  • Flexible PLLs+DLLs

- Frequency adjustment (multiply and division) and phase adjustment

- Supports global clock

 

  • Built-in Flash Programming

-  Instant-on

-  Supports security bit operation

-  Supports AUTO BOOT and DUAL BOOT

 

  • Configuration

- JTAG configuration

- Up to 6 GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

The GW1NZ series of FPGA products offer ultra-low power consumption, instant on, extreme low cost, non-volatile, high security, various packages, and flexible usage. They can be widely used in communication, industry control, consumer (especially mobile and wearable), etc.

 

Features

 

  • Ultra low power consumption

-55nm embedded flash technology

-LV: Supports 1.2V core voltage

-ZV: Supports 0.9V core voltage (below 10uW standby power consumption with Power Management)

-Power Management Module

-Clock dynamically turns on and off

 

  • Power Management Module

-SPMI: System power management interface hard core

 

  • User Flash

-64K bits

-Data Width: 32

- 10,000 write cycles

-Greater than ten years' data retention at +85 ℃

-Supports page erasure: 2048 bytes per page

-Duration: Max. 25ns

-Electric current

a) Read Operation: 2.19 mA/25 ns (VCC) & 0.5 mA/25 ns (VCCX) (MAX);

b) Write operation/erase operation: 12/12 mA(MAX)

-Quick page erasure/Write operation

-Clock frequency: 40MHz

-Write operation time: ≤16μs

-Page erasure time: ≤120 ms

 

  • Multiple I/O Standards

-LVCMOS33/25/18/15/12;LVTTL33, PCI,

-LVDS25E,BLVDSE,MLVDSE,LVPECLE,RSDSE

-Input hysteresis option

-Supports 4mA,8mA,16mA,24mA,etc. drive options

-Slew Rate option

-Output drive strength option

-Individual Bus Keeper, Weak Pull-up, Weak Pull-down, and Open Drain option

-Hot Socket

-I3C hard core, supports SDR mode

 

  • Abundant Slices

-Four input LUT (LUT4)

-Double-edge flip-flops

-Supports shifter register

-Supports shadow SRAM

 

  • Block SRAM with multiple modes

-Supports Dual Port, Single Port, and Semi Dual Port

-Supports bytes write enable

 

  • Flexible PLLs

-Frequency adjustment (multiply and division) and phase adjustment

-Supports global clock

 

  • Built-in Flash programming

-Instant-on

-Supports security bit operation

-Supports AUTO BOOT and DUAL BOOT

 

  • Configuration

-JTAG configuration

-Offers up to six GowinCONFIG configuration modes: AUTOBOOT, SSPI, MSPI, CPU, SERIAL, DUAL BOOT

 


  

GW1NZ Family Table

 

Device GW1NZ-1
LUT4 1,152
Flip-Flop (FF) 864

Shadow SRAM S-SRAM (bits)

4K

Block SRAM B-SRAM (bits)

72K
PLLs + DLLs 1 + 0
User Flash (bits) 64K
VCC 1.2V(LV) / 0.9V(ZV)

 


  

Package Information and Max. User I/O

 

Package

Pitch (mm)

Size (mm) GW1NZ-1
QN32 0.4 4 x 4 25
CS16 0.4 1.8 x 1.8 11

GW1NS Video Training

Click Here

 

 


 

 GW1NS Family Table

 

Parameter GW1NS-2 GW1NS-2C
LUT4 1,728 1,728
FF 1,296 1,296
B-SRAM bits 72K 72K
B-SRAM quantity 4 4
S-SRAM bits 4,608 4,608
Embedded Memory pSRAM (Mb)   32
User Flash bits 1M 1M
PLLs + DLLs 1 + 2 1 + 2
OSC 1, +/- 5% accuracy 1,+/- 5% accuracy
Hard Core Processor - Cortex-M3
USB PHY USB2.0 PHY USB2.0 PHY
ADC Channels 1 1
I/O Banks 4 4
Max. User I/O 95 95
Core Voltage 1.2V 1.2V

 


 

Package Options with Max I/O (Refer to the latest datasheet for details)

 

Package Pitch(mm) Size(mm) GW1NS-2C GW1NS-2
CS36 0.4 2.5 x 2.5 30(6) 30(6) 
QN32 0.5 5 x 5

25(4)

25(4) 
QN32U 0.5 5 x 5 16(2)  16(2)
QN48 0.4 6 x 6 38(7) 38(7)
LQ144 0.5 22 x 22 95(12)  95(12)

 


 

Embedded 32-bit RISC Microprocessor

  • Arm Cortex-M3 (60 MHz)
  • 128K User Flash

 

Embedded ADC

  • 8 Channels
  • 12-bit SAR AD conversion
  • 1 MHz Slew Rate
  • Up to 16 MHz sampling clock

 

Flash Configuration

  • Supports 2 image files
  • Supports Dual Boot
  • Online Upgradeable
  • Remote Upgrade

 

Integrated Development Flow for both M3 Core and FPGA Programming

  • Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one 

 

Embedded USB2.0 PHY

  • 480 Mbps data speed
  • Type-C compatible

 

Fixed MIPI D-PHY I/O

  • I/O's are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution

 

GW1NSR Version includes:

  • 32M-bits of embedded pSRAM memory
  • 8-bit wide, 332Mbps data rates (166 MHz clock)

 

Real-Time Operating Systems Supported

  • uCOSIII
  • FreeRTOS

The GW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates.  It has been optimized with Low Power, Small Size, and Thinnest Package in mind.

 

Features:

  • Embedded 64 Mb pSRAM
  • Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
  • Small package sizes
  • Low power consumption
  • Dual Boot FPGA
  • Remote upgradeable bitstream

 


 

GW1NR Family Table

 

Device GW1NR-4 GW1NR-9
LUT4 4,608 8,640
Flip-Flop (FF) 3,456 6,480
ShadowSRAM S-SRAM(bits) 0 17,280
Block SRAM B-SRAM(bits) 180K 468K
Number of B-SRAM  10 26
User Flash (bits) 256K 608K
SDR SDRAM(bits) 64M 64M
Embedded pSRAM(bits) 64M 64M
18 x 18 Multiplier 16 20
PLLs+DLLs 2+2 2+4
I/O Bank Number 4 4
Max. User I/O 70 120
Core Voltage (LV) 1.2V 1.2V
Core Voltage (UV) 2.5V/3.3V 2.5V/3.3V

 

Package Device Memory
QN88 GW1NR-4/4B SDR SDRAM
QN88 GW1NR-9

SDR SDRAM

PSRAM

MG81 GW1NR-4/4B PSRAM
LQ144 GW1NR-9 PSRAM

 

Package Options and Max I/O (* Refer to the latest datasheet for details)

  

Package Pitch (mm) Size (mm) GW1NR-4  GW1NR-9
QN88 0.4 10 x 10

70(11)

70(17)

LQ144 0.5 22x22 - 120(20)
MG81 0.5 4.5x4.5 68(10)  

GW1N Family Table

 

Device GW1N-1 GW1N-2 GW1N-4 GW1N-6 GW1N-9
LUT4 1,152 2,304 4,606 6,912 8,640
Flip-Flop (FF) 864 1,728 3,456 5,184 6,480
ShadowSRAM S-SRAM(bits) 0 0 0 13,824 17,280
Block SRAM B-SRAM(bits) 72K 180K 180K 468K 468K
Number of B-SRAM  4 10 10 26 26
User Flash (bits) 96K 256K 256K 608K 608K
18 x 18 Multiplier 0 16 16 20 20
PLLs+DLLs 1+0 2+2 2+2 2+4 2+4
I/O Bank Number 4 4 4 4 4
Max. User I/O 119 207 207 273 273
Core Voltage (LV) 1.2V 1.2V 1.2V 1.2V 1.2V
Core Voltage (UV) - 2.5V/3.3V 2.5V/3.3V 2.5V/3.3V 2.5V/3.3V

 


 

Package Options and Max I/O (* Refer latest datasheet for details)

 

Package Pitch (mm) Size (mm2) GW1N-1 GW1N-2 GW1N-4 GW1N-6 GW1N-9
CS30 0.4 2.4 x 2.3 24 - - - -
CM64 0.5 4.1 x 4.1 - - - 55(16) 55(16)
CS72 0.4 3.6 x 3.3 - 57(19) 57(19) - -
QN32 0.5 5 x 5 26 24(3) 24(3) - -
QN48 0.4 6 x 6 41 40(9) 40(9) 40(12) 40(12)
QN88 0.4 10 x 10 - 70(11) 70(11) 70(19) 70(19)
LQ100 0.5 16 x 16 79 79(13) 79(13) 79(20) 79(20)
LQ144 0.5 22 x 22 116 119(22) 119(22) 120(28) 120(28)
LQ176 0.4 22 x 22       147(37) 147(37)
MG160 0.5 8 x 8 - 131(25) 131(25) 131(38) 131(38)
PG204 1.0 17 x 17 - - - - -
PG256 1.0 17 x 17 - 207(32) 207(32) 207(36) 207(36)
PG256M 1.0 17 x 17 - 207(32) 207(32) - -
UG256 0.8 14 x 14       207(36) 207(36)
UG332 0.8 17 x 17 - - - 273(43) 273(43)

LittleBee® Documentation: